Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.16. Virtual Function Registers

The SR-IOV Bridge implements the PCI and PCI Express Configuration Spaces for a maximum of 128 Virtual Functions . The VF registers available are a subset of the PF registers. For example, the VFs do not implement the Link Capabilities 2 register. The definitions of VF registers are the same as PF registers. For additional details, refer to the PCI Express Base Specification 3.0.
Note: The following Virtual Function register map is applicable to all revisions of the Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe from the 18.1 release of Intel® Quartus® Prime onward.
Table 85.   Virtual Function Registers - Differences from PF

Address (hex)

Name

Description

0x000 Vendor ID and Device ID Register Vendor ID Register and Device ID Registers defined in PCI Express Base Specification 3.0 . These registers are hardwired to all 1s.
0x004 Command and Status Register PCI Command and Status Registers. Refer to Command and Status Register for VFs for descriptions of the implemented fields.
0x008 Revision ID and Class Code Register PCI Revision ID and Class Code Registers defined in PCI Express Base Specification 3.0 . The VF has the same settings and access as PF0.
0x00C BIST, Header Type, Latency Timer and Cache Line Size Registers Contains the following registers defined in the PCI Express Base Specification 3.0 : BIST Register, Header Type Register, Latency Timer, Cache Line Size Register. These registers are hardwired to all 0s for VFs.
0x010:

0x028

Reserved N/A
0x02C Subsystem Vendor ID and Subsystem ID Registers PCI Subsystem Vendor ID and Subsystem ID Registers. The VF has the same settings and access as PF0.
0x030 Reserved N/A
0x034 Capabilities Pointer This register points to the first Capability Structure in the PCI Configuration Space. For VFs, it points to the MSI-X capability.
0x038:

0x03C

Reserved N/A

MSI-X Capability Structure

MSI-X Control Register

Contains the MSI-X Message Control Register, Capability ID for MSI-X, and the next capability pointer. The VF has the same fields and access as the parent PF.

MSI-X Table Offset

Points to the MSI-X Table in memory. Also specifies the BAR corresponding to the memory segment where the MSI-X Table resides. The VF has the same fields and access as the PF.

MSI-X PBA Offset

Points to the MSI-X Pending Bit Array in memory. Also, specifies the BAR corresponding to the memory segment where the PBA Array resides. The VF has the same fields and access as the parent PF.

PCI Express Capability Structure

PCI Express Capability List Register

Capability ID, PCI Express Capabilities Register, and the next capability pointer. Refer to cite="PCI Express Capability List Register for VFs" for descriptions of the implemented fields.

PCI Express Device Capabilities Register

PCI Express Device Capabilities Register. The VF Device Capabilities Register supports the same fields as the PF Device Capabilities Register.

PCI Express Device Control and Status Registers

The lower 16 bits implement the PCI Express Device Control Register. The upper 16 bits implement the Device Status Register. Refer to PCI Express Devices Control and Status Registers for VFs for descriptions of the implemented fields.

Link Capabilities Register

A read to any VF with this address returns the Link Capabilities Register settings of the parent PF.

Link Control and Status Registers

This register is not implemented for VFs, and reads as all 0s.

Device Capabilities 2 Registers

A read to any VF with this address returns the Device Capabilities 2 Register settings of the parent PF.

Device Control 2 and Status 2 Registers

This register is not implemented for VFs. A read to this address returns all 0s.

Link Capabilities 2 Register

This register is not implemented for VFs. A read to this address returns all 0s.

Link Control 2 and Status 2 Registers This register contains control and status bits for the PCIe link. For VFs, bit[16] stores the current de-emphasis level setting for the parent PF. All other bits are reserved.

Alternate RID (ARI) Capability Structure

0x100

ARI Enhanced Capability Header

PCI Express Extended Capability ID for ARI and Next Capability pointer. The Next Capability pointer points to NULL.

0x104

ARI Capability Register, ARI Control Register

This register is not implemented for VFs. A read to this address returns all 0s.

Table 86.  Command and Status Register for VFs - 0x004

Bits

Register Description

Default Value

Access

Command Register

[1:0] Reserved. 0 RO
[2] Bus Master enable. When set, the VF can generate transactions as a bus master. 0 RW
[15:3] Reserved. 0 RO

Status Register

[3:0] Reserved. 0 RO
[4] Indicates the presence of PCI Extended Capabilities. This bit is hardwired to 1. 0 RW1C
[7:5] Reserved. 0 RO
[8] Master Data Parity Error. Enabled when the PF PCI Command Register Parity Error Response bit is set. When set, indicates one of the following conditions:
  • The device has received a Poisoned Completion from the link for this VF
  • This VF has transmitted a Poisoned Memory Write request on the link
RW1C
[10:9] Reserved. 0 RO
[11] Signal Target Abort. When set, this VF has sent a Completion to the link with Completer Abort (CA) stats. 0 RW1C
[12] Received Target Abort. When set, indicates that this VF has received a Completion from the link with the CA status. 0 RW1C
[13] Received Master Abort. When set, indicates that this VF has received a Completion from the link with the Unsupported Request (UR) status. 0 RW1C
[14] Signaled System Error. When set, indicates that this VF has transmitted a Fatal or Non-Fatal error message on the link to the Root Complex. Enabled when the PF PCI Command Register SERR Enable bit is set. 0 RW1C
[15] Received Master Abort. When set, indicates the VF has received a Completion from the link with the Unsupported Request (UR) status. 0 RW1C
Table 87.  PCI Express Capability List Register for VFs -

Bits

Register Description

Default Value

Access

[31:19] Hardwired to 0. 2 RO
[18:16] Version ID: Version of PCI Express Capability. 0 RW
[15:8] Next Capability Pointer: Points to NULL. 0 RO
[7:0] Capability ID assigned by PCI-SIG. 0x10 RO
Table 88.  PCI Express Device Control and Status Registers for VFs -

Bits

Register Description

Default Value

Access

Control Register

[14:0] Reserved. 0 RO
[15] Function-Level Reset. Writing a 1 to this bit generates a Function-Level Reset for this VF. Only functional when the PF Device Capabilities Register FLR Capable bit is set. This bit always reads as 0. 0 RW

Status Register

[16] Correctable Error Detected. 0 RW1C
[17] Non-Fatal Error Detected. 0 RW1C
[18] Fatal Error Detected. 0 RW1C
[19] Unsupported Request Detected. 0 RW1C
[20] Not implemented. 0 RO
[21] Transaction Pending. When set, indicates that a Non-Posted request issued by this VF is still pending. 0 RO
[31:22] Reserved. 0 RO

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