Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.13. Advanced Error Capabilities and Control Register

Table 67.  Advanced Error Capabilities and Control Register - 0x118

Bits

Register Description

Default Value

Access

[4:0]

First Error Pointer

0

ROS

[5]

ECRC Generation Capable

Set in Platform Designer

RO

[6]

ECRC Generation Enable

0

RW

[7]

ECRC Check Capable

Set in Platform Designer

RO

[8]

ECRC Check Enable

0

RW

[31:9] Reserved 0 RO

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