Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

2.1. Generating the Example Design Testbench

Follow these steps to generate the SR-IOV DMA example design testbench:

  1. Copy <install_dir>/ ip/altera/altera_pcie/altera_pcie_sriov/example_design/sriov_top_dma_gen3_x8_256b.qsys to your working directory. This top-level Qsys design includes three subsystems.
    Qsys Subsystem Description
    sriov_dma_app_g3x8_256b.qsys This subsystem implements of the Read DMA read and Write DMA modules and the Read and Write Descriptor Controllers. the DMA engine.
    rddc_ctl_256b.qsys This subsystem implements the Read Descriptor Controller for 4 Read DMA channels.
    wrdc_ctl_256b.qsys This subsystem implements the Write Descriptor Controller for 4 Write DMA channels.
  2. Rename the top-level Qsys file, sriov_top_dma_gen3_x8_256b.qsys, to top.qsys.
  3. In your working directory, start Qsys by typing the following command:
    qsys-edit
  4. Open top.qsys.

    The following figure shows the Qsys system.

    Figure 3. Top-Level Qsys System for SR-IOV Gen3 x8 DMA Example Design
  5. On the Generate menu, select Generate Testbench System.
    The Generation dialog box appears.
  6. Specify the following parameters:
    Table 8.  Parameters to Specify on the Generation Menu in Qsys

    Parameter

    Value

    Testbench System

    Create testbench Qsys system

    Standard, BFMs for standard Avalon interfaces.

    Create testbench simulation model

    Verilog. This option generates simulation files for the testbench.

    Allow mixed-language simulation Leave this option off.

    Output Directory

    Path

    working_dir/

    Testbench

    working_dir/testbench/
  7. Click Generate.
    Qsys generates the testbench.
  8. To generate files for compilation, on the Quartus® Prime Generate menu, select Generate HDL.
    The Generation dialog box appears.
  9. Specify the following parameters:
    Table 9.  Parameters to Specify on the Generation Menu in Qsys

    Parameter

    Value

    Verilog

    Create HDL design files for synthesis

    Verilog.

    Create timing and resource estimates for third-party EDA synthesis tools

    Leave this option off.

    Create block symbol file (.bsf) Leave this option on.

    Simulation

    Create simulation model

    None. (You created the simulation model when you generated the testbench.)

    Allow mixed language simulation

    Leave this option off.

    Output Directory

    Path

    working_dir/top
  10. Click Generate.
  11. On the File menu, click Save.

Did you find the information on this page useful?

Characters remaining:

Feedback Message