Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

3.7. PHY Characteristics

Table 19.  PHY Characteristics

Parameter

Value

Description

Gen2 TX de-emphasis

3.5dB

6dB

Specifies the transmit de-emphasis for Gen2. Intel recommends the following settings:

  • 3.5dB: Short PCB traces
  • 6.0dB: Long PCB traces.

Use ATX PLL

On/Off

When enabled, the Hard IP for PCI Express uses the ATX PLL instead of the CMU PLL Using the ATX PLL instead of the CMU PLL reduces the number of transceiver channels that are necessary for Gen1 and Gen2 variants. This option requires the use of the soft reset controller and does not support the CvP flow. For more information about channel placement, refer to .

Enable Common Clock Configuration (for lower latency)

On/Off

When you turn this option on, this component and the component at the opposite end of the Link are operating with a common clock source.

This parameter is only available for the Avalon-ST interface.

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