Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

1.8. Recommended Speed Grades for SR-IOV Interface

Table 7.   Stratix V Recommended Speed Grades for All SR-IOV Configurations Intel recommends setting the Quartus® Prime Analysis & Synthesis Settings Optimization Technique to Speed when the Application Layer clock frequency is 250 MHz. For information about optimizing synthesis, refer to “Setting Up and Running Analysis and Synthesis in Quartus® Prime Help. For more information about how to effect the Optimization Technique settings, refer to Area and Timing Optimization in volume 2 of the Quartus® Prime Handbook. Refer to the Related Links below.

Link Rate

Link Width

Interface Width

Application Clock Frequency (MHz)

Recommended Speed Grades

Gen2

×8

256 bits

125

–1, –2, –3, –4

Gen3

×4

256 bits

125

–1, –2, –3,–4

×8

256 bits

250

–1, –2, –3 2

2 The -4 speed grade is also possible for this configuration; however, it requires significant effort by the end user to close timing.

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