Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

2.2. Understanding the Generated Files and Directories

Table 10.  Qsys Generation Output Files  

Directory

Description

<testbench_dir>/<variant_name>/testbench

Includes testbench subdirectories for the Aldec, Cadence, Mentor, and Synopsys simulation tools with the required libraries and simulation scripts.

<testbench_dir>/<variant_name>/testbench/<cad_vendor>

Includes the HDL source files and scripts for the simulation testbench.

<testbench_dir>/<variant_name>/testbench/<variant_name>_tb/simulation/submodules Includes the HDL files for simulation.

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