Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

3.1. System Settings

Table 11.  System Settings for PCI Express

Parameter

Value

Description

Lane Rate

Gen1 (2.5 Gbps)

Gen2 (2.5/5.0 Gbps)

Gen3 (2.5/5.0/8.0 Gbps) 

Specifies the maximum data rate at which the link can operate.

Number of Lanes

×1, ×2, ×4, ×8

Specifies the maximum number of lanes supported.

Port type

Native Endpoint

Specifies the port type. SR-IOV is only available for the Native Endpoint in the current release.

The Endpoint stores parameters in the Type 0 Configuration Space.

PCI Express Base Specification version

2.1, 3.0 Select either the 2.1 or 3.0 specification.
Application interface Avalon-ST 256-bit

Specifies the width of the Avalon-ST interface to the Application Layer.

Beginning in 16.0, the SR-IOV variant supports only a 256-bit interface. Customers that have mature designs with a 128-bit interface to the Application Layer may continue to use it. Refer to the archived 15.1 documentation, Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions Use Guide, 15.1 available on the Documentation Archive web page.

Reference clock frequency

100 MHz

The PCI Express Base Specification 3.0 requires a 100 MHz ±300 ppm reference clock. The 125 MHz reference clock is provided as a convenience for systems that include a 125 MHz clock source. For more information about Gen3 operation, refer to 4.3.8 Refclk Specifications for 8.0 GT/sin the specification.

For Gen3, Intel recommends using a common reference clock (0 ppm). For designs with separate reference clocks (non 0 ppm), the PCS occasionally must insert SKP symbols, potentially causing the PCIe link to go to recovery. Gen1 and Gen2 modes are not affected by this issue. Systems using the common reference clock (0 ppm) are not affected by this issue. The primary repercussion of this is a slight decrease in bandwidth. On Gen3 x8 systems, this bandwidth impact is negligible. If non 0 ppm mode is required, so that separate reference clocks are being used, please contact Intel for further information and guidance.

RX Buffer credit allocation -performance for received requests

Minimum

Low

Balanced

High

Maximum

Determines the allocation of posted header credits, posted data credits, non-posted header credits, completion header credits, and completion data credits in the 16 KB RX buffer. The 5 settings allow you to adjust the credit allocation to optimize your system. The credit allocation for the selected setting displays in the message pane.

Refer to the Throughput Optimization chapter for more information about optimizing performance. The Flow Control chapter explains how the RX credit allocation and the Maximum payload RX Buffer credit allocation and the Maximum payload size that you choose affect the allocation of flow control credits. You can set the Maximum payload size parameter on the Device tab.

The Message window dynamically updates the number of credits for Posted, Non‑Posted Headers and Data, and Completion Headers and Data as you change this selection.

  • Minimum RX Buffer credit allocation—configures the minimum PCIe specification allowed for non-posted and posted request credits, leaving most of the RX Buffer space for received completion header and data. Select this option for variations where application logic generates many read requests and only infrequently receives single requests from the PCIe link.
  • Low—configures a slightly larger amount of RX Buffer space for non-posted and posted request credits, but still dedicates most of the space for received completion header and data. Select this option for variations where application logic generates many read requests and infrequently receives small bursts of requests from the PCIe link. This option is recommended for typical endpoint applications where most of the PCIe traffic is generated by a DMA engine that is located in the endpoint application layer logic.
  • Balanced—configures approximately half the RX Buffer space to received requests and the other half of the RX Buffer space to received completions. Select this option for variations where the received requests and received completions are roughly equal.
  • High—configures most of the RX Buffer space for received requests and allocates a slightly larger than minimum amount of space for received completions. Select this option where most of the PCIe requests are generated by the other end of the PCIe link and the local application layer logic only infrequently generates a small burst of read requests. This option is recommended for typical root port applications where most of the PCIe traffic is generated by DMA engines located in the endpoints.
  • Maximum—configures the minimum PCIe specification allowed amount of completion space, leaving most of the RX Buffer space for received requests. Select this option when most of the PCIe requests are generated by the other end of the PCIe link and the local application layer logic never or only infrequently generates single read requests. This option is recommended for control and status endpoint applications that don't generate any PCIe requests of their own and only are the target of write and read requests from the root complex.

Enable byte parity ports on Avalon-ST interface

On/Off

When on, the RX and TX datapaths are parity protected. Parity is odd.

This parameter is only available for the Avalon‑ST Stratix V Hard IP for PCI Express.

Enable credit consumed selection port tx_cons_cred_sel

On/Off

When on, the core includes the tx_cons_cred_sel port.

Enable Hard IP reset pulse at power-up when using the soft reset controller

On/Off

When On, the soft reset controller generates a pulse at power up to reset the Hard IP. This pulse ensures that the Hard IP is reset after programming the device, regardless of the behavior of the dedicated PCI Express reset pin, perstn. This option is available for Gen2 and Gen3 designs that use a soft reset controller.

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