Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Document Table of Contents

11.1.1. Changing Between Serial and PIPE Simulation

By default, the Intel testbench runs a serial simulation. You can change between serial and PIPE simulation by editing the top-level testbench file.

For Endpoint designs, the top-level testbench file is <working_dir>/<instantiation_name>/testbench/<instantiation_name>_tb/simulation/<instantiation_name>_tb.v

The serial_sim_hwtcl and enable_pipe32_sim_hwtcl parameters control serial mode or PIPE simulation mode. To change to PIPE mode, change enable_pipe32_sim_hwtcl to 1'b1 and serial_sim_hwtcl to 1'b0.

Table 99.  Controlling Serial and PIPE Simulations
Data Rates Parameter Settings
serial_sim_hwtcl enable_pipe32_sim_hwtcl
Serial simulation 1 0
PIPE simulation 0 1

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