Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.15.2. ARI Enhanced Capability Header

Table 70.  ARI Enhanced Capability ID - 0x200 0x178

Bits

Register Description

Default Value

Default Value

Access

[15:0]

PCI Express Extended Capability ID for ARI.

0x000E

RO

[19:16]

Capability Version.

0x1

RO

[31:20]

When ARI support is enabled, points to SRIOV Capability otherwise points to Null.

0x240

RO

Table 71.  ARI Enhanced Capability Header and Control Register -0x104

Bits

Register Description

Default Value

Access

[0]

Specifies support for arbitration at the Function group level. Not implemented.

0

RO

[7:1] Reserved.

0

RO

[15:8]

ARI Next Function Pointer. Pointer to the next PF.

1

RO

[31:16]

Reserved.

0

RO

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