Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

4.4. BAR Hit Signals

The IP core contains logic that determines which BAR corresponds to a particular TLP for the following types of transactions: memory reads, memory writes and Atomic Ops. This information is sent out via the rx_st_bar_range[2:0] outputs. User application logic can leverage this information to know what BAR the transactions going across the Avalon-ST RX interface are targeting.

Signal

Direction

Description

rx_st_mask Input The Application Layer asserts this signal to tell the Hard IP to stop sending non-posted requests. This signal can be asserted at any time. Up to 10 non-posted requests that can be transferred to the Application Layer after rx_st_mask is asserted.

This signal stalls only non-posted TLPs. All others continue to be forwarded to the Application Layer. The stalled non-posted TLPs are held in the RX buffer until the mask signal is deasserted. They are not discarded. If used in a Root Port mode, asserting the rx_st_mask signal stops all I/O and MemRd and configuration accesses because these are all non-posted transactions.

rx_st_bar_hit_tlp0[7:0]

rx_st_bar_hit_tlp1[7:0]

Output

Identifies the matching BAR for the TLP driven on the Avalon-ST RX interface. Valid for MRd, MWr and Atomic Op TLPs. rx_st_bar_hit_tlp<n>[7:0] should be ignored for all other TLPs.

Valid in the first cycle of a TLP, when rx_st_valid_app and any bit of rx_st_sop_app are asserted. rx_st_bar_hit_tlp0 applies to the TLP that starts on bits [127:0] . rx_st_bar_hit_tlp1 applies to the TLP that starts on bits [255:128].

The following encodings are defined:

  • 0x01: BAR 0 when configured as 32-bit BAR. Or BAR 0-1 when configured as 64-bit BAR.
  • 0x02: BAR 1 when configured as 32-bit BAR. Reserved when BAR 1 is combined with BAR 0 to form a 64-bit BAR.
  • 0x04: BAR 2 when configured as 32-bit BAR. Or BAR 2-3 when configured as 64-bit BAR.
  • 0x08: BAR 3 when configured as 32-bit BAR. Reserved when BAR 2 is combined with BAR 3 to form a 64-bit BAR.
  • 0x10: BAR4 when configured as 32-bit BAR. Or BAR 4-5 when configured as 64-bit BAR.
  • 0x20: BAR5 when configured as 32-bit BAR. Reserved when BAR 4 is combined with BAR 5 to form a 64-bit BAR.
  • 0x40 and 0x80: Reserved.

When rx_st_bar_hit_tlp0 orrx_st_bar_hit_tlp1 indicates the address of a PF, the BAR number above should be interpreted as a PF BAR. When rx_st_bar_hit_tlp0 orrx_st_bar_hit_tlp1provides the address of a VF (indicating a VF hit), the BAR number should be interpreted as a VF BAR.

These signals are required to support multiple packets per cycle. The SR-IOV implementation does not support multiple packets per cycle. Consequently, these signals are not used.

rx_st_bar_hit_fn_tlp0[7:0]

rx_st_bar_hit_fn_tlp1[7:0]

output

Identifies the Function number that was hit by a TLP driven on the Avalon-ST RX interface. These outputs are valid for MRd, MWr and Atomic Op TLPs. Theses and are to be ignored for all other TLPs.

rx_st_bar_hit_fn_tlp<n> is valid in the first cycle of a TLP, when rx_st_valid_app and any bit of rx_st_sop_app are asserted. rx_st_bar_hit_fn_tlp0[7:0] applies to the TLP that starts on bits [127:0]. rx_st_bar_hit_fn_tlp1[7:0] applies to the TLP that starts on bits [255:128].

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