Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

1.1.1. SR-IOV Features

Important changes in the Quartus® Prime 16.0 release:
  • Removed support for new designs using a 128-bit interface to the Application Layer.
  • Mature SR-IOV designs implemented in the 15.0 or 15.1 Quartus® Prime can continue to use the 128-bit interface. Refer to the archived 15.1 documentation, Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions Use Guide, 15.1 available on the Documentation Archive web page. Intel supports only the 256-bit interface to the Application Layer for new designs.
  • Changed the address map for many registers including, SR-IOV and Alternative Routing-ID (ARI) registers. Refer to SR-IOV Registers and Revision History chapters for more information.

The Stratix V Hard IP for PCI Express with SR-IOV supports the following features:

  • Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
  • Support for ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Endpoints. Downtrains to appropriate configuration when plugged into a lower bandwidth configuration, including Gen1 x1, Gen1 x2, and so on.
  • Dedicated 16 kilobyte (KB) receive buffer.
  • Optional hard reset controller for Gen2.
  • Qsys example designs demonstrating parameterization, design modules, and connectivity.
  • Extended credit allocation settings to better optimize the RX buffer space based on application type.
  • End-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.
  • Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions.
  • Support for Gen3 PIPE simulation.
  • Easy to use:
    • Flexible configuration.
    • No license requirement.
    • Example designs to get started.
Table 2.  Feature Comparison for all Hard IP for PCI Express IP CoresThe table compares the features of the three mainstream Hard IP for PCI Express IP Cores. Refer to the Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions User Guide for the features of that variant.

Feature

Avalon-ST Interface

Avalon-MM Interface

Avalon-MM DMA

Avalon-ST with SR-IOV

IP Core License

Free

Free

Free

Free

Native Endpoint

Supported

Supported

Supported

Supported

Legacy Endpoint 1

Supported

Not Supported

Not Supported

Not supported

Root port

Supported

Supported

Not Supported

Not supported

Gen1

×1, ×2, ×4, ×8

×1, ×2, ×4, ×8

Not Supported

Not supported

Gen2

×1, ×2, ×4, ×8

×1, ×2, ×4, ×8

×4, ×8

×8

Gen3

×1, ×2, ×4, ×8

×1, ×2, ×4

×4, ×8

×4, ×8

64-bit Application Layer interface

Supported

Supported

Not supported

Not supported

128-bit Application Layer interface

Supported

Supported

Supported

Not supported

256‑bit Application Layer interface

Supported

Not Supported

Supported

Supported

Maximum payload size

128, 256, 512, 1024, 2048 bytes

128, 256 bytes

128, 256 bytes

128, 256 bytes

Number of tags supported for non-posted requests

256

8

16

256

62.5 MHz clock

Supported

Supported

Not Supported

Not supported

Automatically handle out-of-order completions (transparent to the Application Layer)

Not supported

Supported

Not Supported

Not supported

Automatically handle requests that cross 4 KB address boundary (transparent to the Application Layer)

Not supported

Supported

Supported

Not supported

Polarity Inversion of PIPE interface signals

Supported

Supported

Supported

Supported

ECRC forwarding on RX and TX

Supported

Not supported

Not supported

Not supported

Number of MSI requests

1, 2, 4, 8, 16, or 32

1, 2, 4, 8, 16, or 32

1, 2, 4, 8, 16, or 32

1, 2, 4, 8, 16, or 32 (for Physical Functions)

MSI-X

Supported

Supported

Supported

Supported

Legacy interrupts

Supported

Supported

Supported

Supported

Expansion ROM

Supported

Not supported

Not supported

Not supported
PCIe bifurcation Not supported Not supported Not supported  
Table 3.  TLP Support Comparison for all Hard IP for PCI Express IP CoresThe table compares the TLP types that the four Hard IP for PCI Express IP Cores can transmit. Each entry indicates whether this TLP type is supported (for transmit) by endpoints (EP), Root Ports (RP), or both (EP/RP).

Transaction Layer Packet type (TLP) (transmit support)

Avalon-ST Interface

Avalon-MM Interface

Avalon-MM DMA

Avalon-ST with SR-IOV
Memory Read Request (Mrd) EP/RP EP/RP EP EP
Memory Read Lock Request (MRdLk) EP/RP   EP EP
Memory Write Request (MWr) EP/RP EP/RP EP EP
I/O Read Request (IORd) EP/RP EP/RP   EP
I/O Write Request (IOWr) EP/RP EP/RP   EP
Config Type 0 Read Request (CfgRd0) RP RP   EP
Config Type 0 Write Request (CfgWr0) RP RP   EP
Config Type 1 Read Request (CfgRd1) RP RP   EP
Config Type 1 Write Request (CfgWr1) RP RP   EP
Message Request (Msg) EP/RP EP/RP   EP
Message Request with Data (MsgD) EP/RP EP/RP   EP
Completion (Cpl) EP/RP EP/RP EP EP
Completion-Locked (CplLk) EP/RP     EP
Completion Lock with Data (CplDLk) EP/RP     EP
Fetch and Add AtomicOp Request (FetchAdd) EP      

The Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions User Guide explains how to use this IP core and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this document only in conjunction with an understanding of the PCI Express Base Specification.

Note: This release provides separate user guides for the different variants. The Related Information provides links to all versions.
1 Not recommended for new designs.

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