Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.11. Correctable Error Status Register

Table 65.  Correctable Error Status Register -0x110

Bits

Register Description

Default Value

Access

[31:14] Reserved 0

RO

[13]

When set, indicates an Advisory Non-Fatal Error

0

RW1C

[12]

When set, indicates a Replay Timeout

0

RW1C

[11:9]

Reserved

0

RO

[8]

When set, indicates a Replay Number Rollover

0

RW1C

[7]

When set, indicates a Bad DLLP received

0

RW1C

[6]

When set, indicates a Bad TLP received 0

RW1C

[5:1]

Reserved

0

RO

[0]

When set, indicates a Receiver Error

0

RW1C

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