Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

4.14.1. Physical Layout of Hard IP In Stratix V Devices

Stratix V devices include one, two, or four Hard IP for PCI Express IP cores. The following figures illustrate the placement of the PCIe IP cores, transceiver banks, and channels for the largest Stratix V devices. Note that the bottom left IP core includes the CvP functionality. The other Hard IP blocks do not include the CvP functionality.
Figure 23.  Stratix V Devices with Four PCIe Hard IP Blocks

Smaller devices include the following PCIe Hard IP Cores:

  • One Hard IP for PCIe IP core - bottom left IP core with CvP, located at GX banks L0 and L1
  • Two Hard IP for PCIe IP cores - bottom left IP core with CvP and bottom right IP Core, located at banks L0 and L1, and banks R0 and R1

Refer to Stratix V GX/GT Channel and PCIe Hard IP (HIP) Layout for comprehensive information on the number of Hard IP for PCIe IP cores available in various Stratix V packages.

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