Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

7.3. Transaction Layer Errors

Table 92.  Errors Detected by the Transaction Layer

Error

Type

Description

Poisoned TLP received

Uncorrectable (non-fatal)

This error occurs if a received Transaction Layer Packet has the EP poison bit set.

The received TLP is passed to the Application Layer and the Application Layer logic must take appropriate action in response to the poisoned TLP. Refer to “2.7.2.2 Rules for Use of Data Poisoning” in the PCI Express Base Specification for more information about poisoned TLPs.

Unsupported Request for Endpoints

Uncorrectable (non-fatal)

This error occurs whenever a component receives any of the following Unsupported Requests:

  • Type 0 Configuration Requests for a non-existing function.
  • Completion transaction for which the Requester ID does not match the bus, device and function number.
  • Unsupported message.
  • A Type 1 Configuration Request TLP for the TLP from the PCIe link.
  • A locked memory read (MEMRDLK) on native Endpoint.
  • A locked completion transaction.
  • A 64-bit memory transaction in which the 32 MSBs of an address are set to 0.
  • A memory or I/O transaction for which there is no BAR match.
  • A memory transaction when the Memory Space Enable bit (bit [1] of the PCI Command register at Configuration Space offset 0x4) is set to 0.
  • A poisoned configuration write request (CfgWr0)

In all cases the TLP is deleted in the Hard IP block and not presented to the Application Layer. If the TLP is a non-posted request, the Hard IP block generates a completion with Unsupported Request status.

Completion timeout

Uncorrectable (non-fatal)

This error occurs when a request originating from the Application Layer does not generate a corresponding completion TLP within the established time. It is the responsibility of the Application Layer logic to provide the completion timeout mechanism. The completion timeout should be reported from the Transaction Layer using the cpl_err[0] signal.

Completer abort  (1)

Uncorrectable (non-fatal)

The Application Layer reports this error using the cpl_err[2]signal when it aborts receipt of a TLP.

Unexpected completion

Uncorrectable (non-fatal)

This error is caused by an unexpected completion transaction. The Hard IP block handles the following conditions:

  • The Requester ID in the completion packet does not match the Configured ID of the Endpoint.
  • The completion packet has an invalid tag number. (Typically, the tag used in the completion packet exceeds the number of tags specified.)
  • The completion packet has a tag that does not match an outstanding request.
  • The completion packet for a request that was to I/O or Configuration Space has a length greater than 1 dword.
  • The completion status is Configuration Retry Status (CRS) in response to a request that was not to Configuration Space.

In all of the above cases, the TLP is not presented to the Application Layer; the Hard IP block deletes it.

The Application Layer can detect and report other unexpected completion conditions using the cpl_err[2] signal. For example, the Application Layer can report cases where the total length of the received successful completions do not match the original read request length.

Receiver overflow   (1)

Uncorrectable (fatal)

This error occurs when a component receives a TLP that violates the FC credits allocated for this type of TLP. In all cases the hard IP block deletes the TLP and it is not presented to the Application Layer.

Flow control protocol error (FCPE)  (1)

Uncorrectable (fatal)

This error occurs when a component does not receive update flow control credits with the 200 µs limit.

Malformed TLP

Uncorrectable (fatal)

This error is caused by any of the following conditions:

  • The data payload of a received TLP exceeds the maximum payload size.
  • The TD field is asserted but no TLP digest exists, or a TLP digest exists but the TD bit of the PCI Express request header packet is not asserted.
  • A TLP violates a byte enable rule. The Hard IP block checks for this violation, which is considered optional by the PCI Express specifications.
  • A TLP in which the type and length fields do not correspond with the total length of the TLP.
  • A TLP in which the combination of format and type is not specified by the PCI Express specification.
  • A request specifies an address/length combination that causes a memory space access to exceed a 4  KB boundary. The Hard IP block checks for this violation, which is considered optional by the PCI Express specification.
  • Messages, such as Assert_INTX, Power Management, Error Signaling, Unlock, and Set Power Slot Limit, must be transmitted across the default traffic class.

The Hard IP block deletes the malformed TLP; it is not presented to the Application Layer.

Note:

  1. Considered optional by the PCI Express Base Specification Revision.