Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

4.5. Configuration Status Interface

The output signals listed below drive the settings of the various configuration register fields of the Functions. These settings are often needed in designing Application Layer logic.

Table 25.  Configuration Status Interface

Signal

Direction

Description

bus_num_f0[7:0]

Output

Direction

Bus number assigned to Physical Function 0 by the Root Complex. Captured from CfgWr transactions.

When ARI is enabled, the Application Layer must use this bus number for all TLP requests and completions. When ARI is not enabled, the Application Layer must use this bus number for TLP requests and completions from PF0 and its associated Virtual Functions.

bus_num_f1[7:0]

Output

Bus number assigned to Physical Function 1 by the Root Complex, Captured from CfgWr transactions.

When ARI is enabled,bus_num_f1 is not used. When ARI is not enabled, the application layer must use this bus number for TLP requests and completions from PF1 and its associated Virtual Functions.

device_num_f0[4:0]

Output

Device number assigned to Physical Function 0 by the Root Complex, as captured from CfgWr transactions.

When ARI is enabled, the Requester ID only consists of bus number and function number. Consequently, device_num_f0 is unused. When ARI is disabled, the Application Layer must use device_num_f0 for all TLP requests and completions from PF0 and its associated VFs.

device_num_f1[4:0]

Output

Device number assigned to Physical Function 1 by the Root Complex, as captured from CfgWr transactions.

When ARI is enabled, the Requester ID only consists of bus number and function number. Consequently, device_num_f1 is unused. When ARI is disabled, the Application Layer must use device_num_f1 for all TLP requests and completions from PF0 and its associated VFs.

mem_space_en_pf[<n>-1:0]

Output

The PF Command Registers drive the Memory Space Enable bit. <n> is the number of PFs.

bus_master_en_pf[<n>-1:0]

Output

The PF Command Registers drive the Bus Master Enable bit. <n> is the number of PFs.

mem_space_en_vf[<n>-1:0]

Output

The PF Control Registers drive the SR-IOV Memory Space Enable bit. <n> is the number of PFs.

bus_master_en_vf[<n>-1:0]

Output

The VF<n> Memory Space Enable bit of the PCI Command Register drives bit <n> of this bus. <n> is the total number of VFs.

pf0_num_vfs[7:0]

Output

This output drives the value of the NumVFs register in the PF0 SR-IOV Capability Structure.

pf1_num_vfs[7:0]

Output

This output drives the value of the NumVFs register in the PF1 SR-IOV Capability Structure .

max_payload_size[2:0]

Output

When only PF0 is present, the max payload size field of the PF0 PCI Express Device Control Register drives this output. When more PFs are present, the minimum value of the max payload size field of the PCI Express Device Control Registers drives this output.

rd_req_size[2:0]

Output

When only PF 0 is present, the max read request size field of PF0 PCI Express Device Control Register drives this output. When more PFs are present, the minimum value of the max read request size fields of the PCI Express Device Control Registers drives this output.

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