Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.15.4. Initial VFs and Total VFs Registers

Table 75.  Initial VFs and Total VFs Registers - 0x24C

Bits

Description

Default Value

Access

[15:0]

Initial VFs. Specifies the initial number of VFs configured for this PF.

Same value as TotalVFs

RO

[31:16]

Total VFs. Specifies the total number of VFs attached to this PF.

Set in Platform Designer

RO
Table 76.  Function Dependency Link and NumVFs Registers -0x250

Bit Location

Description

Default Value

Access

[15:0]

NumVFs. Specifies the number of VFs enabled for this PF. Writable only when the VF Enable bit in the SR-IOV Control Register is 0.

0

RW

[31:16]

Function Dependency Link

0

RO

Table 77.  VF Offset and Stride Registers -0x254

Bits

Register Description

Default Value

Access

[15:0]

VF Offset. Specifies the offset of the first VF’s Routing ID with respect to the Routing ID of its PF. The offset is configured for PF0 and PF1 based on the number of VFs and whether ARI is in use. The following offsets are used:

  • Single-Function with no ARI: VF Offset = 1.
  • Two PFs with no ARI: VF Offset = 2 for PF0. 1+ PF0_VF_COUNT for PF1.
  • With ARI: VF Offset = 128 for PF 0. 127+ PF0_VF_COUNT for PF 1.

Refer to description

RO

[31:16]

VF Stride

1

RO

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