Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.8. Uncorrectable Error Status Register

This register controls which errors are forwarded as internal uncorrectable errors. All of the errors are severe and may place the device or PCIe link in an inconsistent state.

Table 62.  Uncorrectable Error Status Register - 0x104

Bits

Register Description

Default Value

Access

[31:21]

Reserved.

0

RO

[20] When set, indicates an Unsupported Request Received 0

RW1C

[19] When set, indicates an ECRC Error Detected 0

RW1C

[18] When set, indicates a Malformed TLP Received 0

RW1C

[17] When set, indicates Receiver Overflow 0

RW1C

[16]

When set, indicates an unexpected Completion was received

0

RW1C

[15]

When set, indicates a Completer Abort (CA) was transmitted

0

RW1C

[14]

When set, indicates a Completion Timeout

0

RW1C

[13]

When set, indicates a Flow Control protocol error

0

RW1C

[12]

When set, indicates that a poisoned TLP was received

0

RW1C

[11:5]

Reserved 0

RO

[4]

When set, indicates a Data Link Protocol error

0

RW1C

[3:0]

Reserved

0

RO

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