Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

Application Layer Clock Frequency for All Combinations of Link Width, Data Rate and Application Layer Interface WidthsThe coreclkout_hip signal is derived from pclk. The following table lists frequencies for coreclkout_hip, which are a function of the link width, data rate, and the width of the Application Layer to Transaction Layer interface. The frequencies and widths specified in this table are maintained throughout operation. If the link downtrains to a lesser link width or changes to a different maximum link rate, it maintains the frequencies it was originally configured for as specified in this table. (The Hard IP throttles the interface to achieve a lower throughput.)

Link Width

Max Link Rate

Avalon Interface Width

coreclkout_hip

×8

Gen1

128

125 MHz

×4

Gen2

128

125 MHz

×8

Gen2

128

250 MHz

×8

Gen2

256

125 MHz

×2

Gen3

128

125 MHz

×4

Gen3

128

250 MHz

×4

Gen3

256

125 MHz

×8

Gen3

256

250 MHz

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