6.5. User-controlled Accesses to the HBM2 Controller
For information on using the APB interface signals, refer to User APB Interface Timing.
Each physical HBM2 channel is mapped to its own sideband register space. The APB address accesses are byte-address based. If a write is issued to an unaligned address, it is ignored (that is, read returns 0 and write has no effect.) The sideband register map is shared between the two HBM2 Pseudo Channels and the allocation of addresses is organized as follows:
- Registers common to both Pseudo-Channels:
Note: The register bit descriptions of Pseudo Channel 0 (PC0) and Pseudo Channel 1 (PC1) in the registers common to both Pseudo Channels apply to the bottom HBM2 interface. For the top HBM2 interface, the PC0 and PC1 register bit definitions are swapped.
- Address map – 16’h0000-16’h00FF.
- Includes Refresh (per-bank, all banks), Self-Refresh, Temperature Readout and Power down status.
- Register Map for individual Pseudo Channels:
Note: The register address maps for individual Pseudo Channel 0 (PC0) and Pseudo Channel 1 (PC1) as shown above apply to the bottom HBM2 interface. For the top HBM2 interface, the PC0 and PC1 register address maps are swapped.
- Address map – Pseudo Channel 0 (16’h0100- 16’h01FF) and Pseudo Channel 1 (0x200-0x2FF).
- This map is used to access ECC and Interrupt Status Registers for each Pseudo Channel.
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