High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 9/27/2021
Public
Document Table of Contents

4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP

The Example Designs tab allows you to configure example design files for simulation and synthesis.
Figure 11. Example Designs tab of HBM2 IP Parameters
Table 15.  Group: Example Designs / Example Design Files
Display Name Description
Simulation

Specifies that the system generate all necessary file sets for simulation when you click Generate Example Design. Expect an additional 1-2 minute delay when generating the simulation fileset.

If you do not enable this parameter, the system does not generate simulation file sets. Instead, the output directory contains the ed_sim.qsys file which contains details of the simulation example design for Platform Designer, and a make_sim_design.tcl file with other corresponding tcl files.

You can run the make_sim_design.tcl file from a command line to generate a simulation example design. The generated example designs for various simulators reside in the /sim subdirectory.

Synthesis

Specifies that the system generate all necessary file sets for synthesis when you click Generate Example Design. Expect an additional 1-2 minute delay when generating the synthesis file set.

If you do not enable this parameter, the system does not generate synthesis file sets. Instead, the output directory contains the ed_synth.qsys file which contains details of the synthesis example design for Platform Designer, and a make_qii_design.tcl file with other corresponding tcl files.

You can run the make_qii_design.tcl file from a command line to generate a synthesis example design. The generated example design resides in the /qii subdirectory.

Tip: The example design supports generation, simulation, and Intel® Quartus® Prime compilation flows for any selected device. To use the example design for simulation, enable the Simulation parameter. To use the example design for compilation and hardware, enable the Synthesis parameter.

Table 16.  Group: Example Designs / Generated HDL Format
Display Name Description
Simulation HDL format

Format of HDL files generated for simulating the design example.

Did you find the information on this page useful?

Characters remaining:

Feedback Message