High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 1/20/2023
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6.5.3. Controller Idle State Status

User logic can read the HBM2 controller idle status values from APB address 16'h000E.
Table 36.  Controller Idle Status Information
Read Data Bit Definition Description
[0] Read Command Queue Idle for PC0.
[1] Read Command Queue Idle for PC1.
[2] Write Command Queue Idle for PC0.
[3] Write Command Queue Idle for PC1.
[4] PC0 Timer Idle.
[5] PC1 Timer Idle.
[7:6] Reserved.
[8] PC0 AXI Read Data Idle.
[9] PC1 AXI Read Data Idle.
[10] PC0 AXI Write Data Idle.
[11] PC1 AXI Write Data Idle.
[15:12] Reserved.