High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

Download
ID 683189
Date 9/27/2021
Public
Document Table of Contents

6.5.3. Controller Idle State Status

User logic can read the HBM2 controller idle status values from APB address 16'h000E.
Table 36.  Controller Idle Status Information
Read Data Bit Definition Description
[0] Read Command Queue Idle for PC0.
[1] Read Command Queue Idle for PC1.
[2] Write Command Queue Idle for PC0.
[3] Write Command Queue Idle for PC1.
[4] PC0 Timer Idle.
[5] PC1 Timer Idle.
[7:6] Reserved.
[8] PC0 AXI Read Data Idle.
[9] PC1 AXI Read Data Idle.
[10] PC0 AXI Write Data Idle.
[11] PC1 AXI Write Data Idle.
[15:12] Reserved.

Did you find the information on this page useful?

Characters remaining:

Feedback Message