High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 9/27/2021
Public
Document Table of Contents

6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram

The following figure shows a high-level block diagram of the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP per Pseudo Channel. The IP communicates with user logic through the AXI protocol.
Figure 15. High Level Block Diagram of HBM2 Implementation

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