High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 9/27/2021
Public
Document Table of Contents

6.2.7. Sideband APB Interface

The sideband APB interface allows user logic to issue refresh commands and also provides access to the controller status signals. Each HBM2 channel has one APB Interface.
Table 27.  APB Interface Signals
Port Name Width Direction Description
ur_paddr 16 Input APB address bus. You can use the APB address bus to access the MMR register space, to issue specific user-requested commands.
ur_psel 1 Input Select. The user interface generates this signal to indicate that the channel APB interface is selected and that a data transfer is required. There is a PSEL signal for each HBM2 channel APB interface and this signal can be tied HIGH.
ur_penable 1 Input Enable. This signal indicates the start of an APB transfer.
ur_pwrite 1 Input Write/Read access. When this signal is HIGH, it indicates an APB write access. When this signal is LOW, it indicates an APB read access.
ur_pwdata 16 Input Write data. This signal is driven by user logic during write cycles when PWRITE is HIGH.
ur_pstrb 2 Input Write strobes (byte enables). This signal indicates which byte lanes to update during a write transfer. There is one write strobe for each eight bits of the write data bus. Write transfers to the HBM2 controller require both the byte enables to be active and hence must be driven to 2’b11. Write strobes must not be active during a read transfer.
ur_prready 1 Output Ready. This signal indicates the completion of a write or read transaction.
ur_prdata 16 Output Read data. The read data bus provides useful HBM2 controller information and status signals.

Did you find the information on this page useful?

Characters remaining:

Feedback Message