High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: duf1511204700090
Ixiasoft
Visible to Intel only — GUID: duf1511204700090
Ixiasoft
7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency
Read latency includes the controller command path latency to issue the read command to the HBM2 memory, memory read latency, and the delay in the read data path through the HBMC memory controller. Simulation reports the minimum latency in AXI core clock cycles seen during the simulation time.