High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 9/27/2021
Public
Document Table of Contents

6.5.6.3. Error Valid Status

You can read individual status signals from address 16’h0104 for Pseudo Channel 0 and 16’h0204 for Pseudo Channel 1. You can also write to these addresses to clear the status signals.

The above addresses provide the actual status signal for the following error conditions:

  • Single bit/Double bit error value from the HBM2 memory
  • Read data/Write Data parity error value from the HBM2 memory.
  • Address/Command parity value.
  • CATTRIP signal.
  • Calibration error signal.
  • Single-bit error and double-bit error from internal RAM used for Write and Read data storage.

To clear the individual Error Valid Signals, write 1’b1 to clear the Valid signal and the corresponding Error Counter.

Table 41.  Read Data Definition for Error Valid Status
Read Data Bit Definition Definition
[0]

DRAM Single-Bit-Error Valid. Asserted when single-bit error occurs and stays high until cleared. Write 1’b1 to clear.

You can retrieve the number of single-bit errors from the single-bit error counter. Clearing the counter does not clear this valid bit or vice-versa. You must issue a separate write command to valid and counter to clear both registers.
[1]

DRAM Double-Bit-Error Valid. Asserted when double-bit error occurs and stays high until cleared. Write 1’b1 to clear.

You can retrieve the number of double-bit errors from the double-bit error counter. Clearing the counter does not clear this valid bit or vice-versa. You must issue a separate write command to valid and counter to clear both registers.
[2]

Read Data Parity Error Valid. Asserted when a Read Data parity error occurs and stays high until cleared. Write 1’b1 to clear.

You can retrieve the number of Read Data parity errors from the Read Data parity error counter. Clearing the counter does not clear this valid bit or vice-versa. You must issue a separate write command to valid and counter to clear both registers.
[3] Write Data Parity Error Valid. Asserted when a Write Data parity error occurs and stays high until cleared. Write 1’b1 to clear.
[4] Address Command Parity Error Valid. Asserted when an Address Command parity error occurs and stays high until cleared. Write 1’b1 to clear.
[5] Cat Trip Error Valid. Asserted when a Cat Trip error occurs and stays high until cleared. Write 1’b1 to clear.
[6] Calibration Error Valid. Asserted when a calibration error occurs and stays high until cleared. Write 1’b1 to clear.
[7] Write SRAM Single-Bit Error Valid. Asserted when a Write SRAM Single-Bit error occurs and stays high until cleared. Write 1’b1 to clear.
[8]

Write SRAM Double-Bit Error Valid. Asserted when a Write SRAM Double-Bit error occurs and stays high until cleared. Write 1’b1 to clear.

[9] Read SRAM Single-Bit Error Valid. Asserted when a Read SRAM Single-Bit error occurs and stays high until cleared. Write 1’b1 to clear.
[10]

Read SRAM Double-Bit Error Valid. Asserted when a Read SRAM Double-Bit error occurs and stays high until cleared. Write 1’b1 to clear.

[15:11] Reserved.

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