High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 9/27/2021
Public
Document Table of Contents

7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth

For each HBM2 DRAM in an Intel® Stratix® 10 device, there are eight channels of 128-bits each. The following example illustrates the calculation of bandwidth offered by one HBM2 interface.

Assuming an interface running at 1 GHz: 128 DQ * 1 GHz = 128 Gbps:

  • The interface operates in double data-rate mode, so the total bandwidth per HBM2 is: 128 Gbps * 2 = 256 Gbps
  • The total bandwidth for the HBM2 interface is: 256 Gbps * 8 = 256 GBytes/sec
  • If the HBM2 controller operates at 90% efficiency, the effective bandwidth is: 256 Gbps * 0.9 = ~230 GByte/sec

Did you find the information on this page useful?

Characters remaining:

Feedback Message