High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

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ID 683189
Date 9/27/2021
Public
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5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator

  1. Navigate to: project_directory>/sim/ed_sim/xcelium.
  2. Type sh xcelium_setup.sh to launch the Xcelium simulator.
  3. To view the simulation results, write the output to a log file. The simulation log provides efficiency data and other useful information.

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