High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 9/27/2021
Public
Document Table of Contents

4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP

Figure 8. FPGA I/O Tab
Table 10.  FPGA I/O Parameters
Display Name Description
Memory PLL Reference clock I/O standard Specifies the I/O standard for the PLL reference clock of the memory interface. The termination options available are LVDS with on-chip termination and LVDS without on-chip termination. This parameter is available beginning with Intel® Quartus® Prime software version 20.3. For designs migrating from previous releases, LVDS without on-chip termination is selected.

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