High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 9/27/2021
Public
Document Table of Contents

2.4. Intel® Stratix® 10 HBM2 Controller Features

Intel® Stratix® 10 FPGAs offer the following controller features.
  • User applications communicate with the HBMC using the AXI4 Protocol.
  • There is one AXI4 interface per HBM2 Pseudo Channel. Each HBM2 interface supports a maximum of sixteen AXI4 interfaces to the sixteen Pseudo Channels. An optional Avalon® interface is supported to each Pseudo Channel from the Intel® Quartus® Prime software.
  • The user interface can operate at a frequency lower than the HBM2 interface frequency. The maximum supported HBM2 interface frequency depends on the FPGA device speed grade. The minimum frequency of the core clock is one quarter of the HBM2 interface frequency.
  • Each AXI interface supports a 256-bit Write Data interface and a 256-bit Read Data interface.
  • The controller offers 32B and 64B access granularity supporting burst length 4 (BL 4) and pseudo-BL 8 (two back to back BL4).
  • The controller offers out-of-order command scheduling and read data reordering.
  • The controller supports user-initiated Refresh commands, and access to the HBM2 channel status registers, through the side band Advanced Peripheral Bus (APB) interface.
  • The controller supports data mask or error correction code (ECC). When you do not use data mask or ECC, you may use those bits as additional data bits.

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