High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

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ID 683189
Date 1/20/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 2. Introduction to High Bandwidth Memory 3. Intel® Stratix® 10 HBM2 Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface 7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance 8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives 9. Document Revision History for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2 in Intel® Stratix® 10 Devices 2.2. HBM2 DRAM Structure 2.3. Intel® Stratix® 10 HBM2 Features 2.4. Intel® Stratix® 10 HBM2 Controller Features
3. Intel® Stratix® 10 HBM2 Architecture x
3.1. Intel® Stratix® 10 HBM2 Introduction 3.2. Intel® Stratix® 10 UIB Architecture 3.3. Intel® Stratix® 10 HBM2 Controller Architecture
3.3. Intel® Stratix® 10 HBM2 Controller Architecture x
3.3.1. Intel® Stratix® 10 HBM2 Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
4.1. Creating an Intel® Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.3. Pin Planning for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.4. Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.6. Register Map IP-XACT Support for HBM2 IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design 5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa* 5.3. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Synopsys VCS* 5.4. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Riviera-PRO* 5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator 5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency 5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface x
6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram 6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals 6.3. User AXI Interface Timing 6.4. User APB Interface Timing 6.5. User-controlled Accesses to the HBM2 Controller 6.6. Soft AXI Switch
6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals x
6.2.1. Clock Signals 6.2.2. Reset Signals 6.2.3. Calibration Status Signals 6.2.4. Memory Interface Signals 6.2.5. User-interface Signals 6.2.6. AXI User-interface Signals 6.2.7. Sideband APB Interface 6.2.8. Avalon® Memory-Mapped (AVMM) Interface Signals
6.3. User AXI Interface Timing x
6.3.1. AXI Write Transaction 6.3.2. AXI Read Transaction 6.3.3. Improving User Logic to HBM2 Controller AXI Interface Timing Controller Backpressure Latency Using AXI Backpressure Latency Using the Early READY Signal to Facilitate Timing Closure Write Response and Read Data Interface Timing
6.4. User APB Interface Timing x
6.4.1. Advanced Peripheral Bus Protocol 6.4.2. APB Interface Timing
6.5. User-controlled Accesses to the HBM2 Controller x
6.5.1. User-controlled Refreshes 6.5.2. Temperature and Calibration Status Readout 6.5.3. Controller Idle State Status 6.5.4. Power Down Status 6.5.5. ECC Error Status 6.5.6. User Interrupt 6.5.7. ECC Error Correction and Detection
6.5.6. User Interrupt x
6.5.6.1. Interrupt Enable and Conditions for Interrupt Generation 6.5.6.2. Interrupt Status 6.5.6.3. Error Valid Status
6.6. Soft AXI Switch x
6.6.1. AXI Switch Selection in HBM2 IP Catalog GUI
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance x
7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth 7.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency 7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency 7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing 7.5. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. Introduction to High Bandwidth Memory
3. Intel® Stratix® 10 HBM2 Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance
8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives
9. Document Revision History for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

6.3.3. Improving User Logic to HBM2 Controller AXI Interface Timing

The HBM2 IP provides a non-zero cycle latency backpressure feature that can improve core timing and usability of the HBM2 IP from the AXI Write Address, Read Address and Write Data Interface. You can enable this feature through the parameter editor.

Controller Backpressure Latency

The Controller Backpressure Latency feature allows the user interface to interface to the controller READY signals (address write, address read and write channels) with flexibility. When you enable this feature, the READY signals provided by the HBM2 controller are issued early, according to a value that you specify.

By default, this feature is disabled, with a backpressure latency of 0 clock cycles. When you enable this feature, you specify a desired backpressure latency of 1 or 2 clock cycles. The READY signals provided by the HBM2 controller — AXI Write Address Ready (AXI_X_Y_AWREADY), AXI Read Address Ready (AXI_X_Y_ARREADY) and AXI Write Data Ready (AXI_X_Y_WREADY) — are then issued early by the number of cycles that you specified.

When this feature is enabled, set to N cycles (supported clock cycle values for N are 1, 2 when the feature is enabled and 0 when disabled), the READY signals provided by the HBM2 Controller (that is, AXI Write Address Ready (AXI_X_Y_AWREADY), AXI Read Address Ready (AXI_X_Y_ARREADY) and AXI Write Data Ready (AXI_X_Y_WREADY)) are issued N clock cycles early. Controller Backpressure Latency is enabled across all the AXI interfaces for the selected HBM2 interface.

Figure 25. AXI Backpressure Latency Selection

When you choose a non-zero backpressure register value, you can choose to add the register stages in either of the following ways:

  • You can allow the HBM2 IP to add the registers in the soft logic adaptor on the AXI interface; this is the default behavior.
  • You can handle the AXI interface timing (early READY deassertion) manually, by disabling the Automatically instantiate back pressure registers within HBM2 IP option.

Using AXI Backpressure Latency

The following timing diagram illustrates backpressure latency of two clock cycles. This value enables the deassertion of the READY signals to happen two core clock cycles earlier than otherwise. Backpressure latency of 2 clock cycles provides the user interface two additional clock cycles to respond to the READY deassertion by continuing to provide valid Write Address/Write Data and Read Address for two clock cycles after the READY deassertion.

As illustrated in the diagram below, with backpressure latency of two clock cycles, READY deasserts in clock cycle T4; however, the HBM2 controller continues to accept input in clock cycles T4 and T5 (input D and E) provided that the corresponding VALID signal is active.

Figure 26. Early Controller READY Deassertion Using Backpressure Latency

Using the Early READY Signal to Facilitate Timing Closure

When you specify a non-zero AXI backpressure latency of N, you can also add a total of N pipeline registers in the AXI interface outputs and the READY inputs from the HBM2 controller. By ensuring the total pipeline registers added in both Input and Output directions is N, you can ease timing closure. You can enable the HBM2 IP to generate these registers from the HBM2 IP parameter editor.

Beginning in the Intel® Quartus® Prime software version 19.4, the HBM2 IP adds the following registers based on the Backpressure latency setting; it is no longer necessary to manually insert the registers.

  • When Backpressure latency is set to 1, the controller deasserts the READY signal one clock cycle early. A single register stage is added in signals in the AXI Interface Valid path from the core to the HBM2 controller.
  • When Backpressure latency is set to 2, the controller deasserts the READY signal two clock cycles early. The HBM2 IP adds the following registers:
    • One register stage is added on the AXI Interface Valid and all related AXI interface signals from the user logic.
    • One register stage is added on READY signals (AWREADY, WREADY, ARREADY) from the controller to the core.

The following figure illustrates the backpressure register placement in the data path between the user core logic and the AXI soft logic adaptor to facilitate timing closure.

Figure 27. Non-zero Latency Backpressure Implementation

Write Response and Read Data Interface Timing

When you enable the read and write response backpressure feature, Write response and Read data interface timing must still be treated at zero cycle latency. The user-interface-issued BREADY and RREADY must be driven HIGH to ensure the controller can provide the outputs when applicable.

When you disable the read and write response backpressure feature, you can add pipeline registers to read and write response outputs, because BREADY and RREADY are always HIGH, indicating that the user interface is ready to accept response at any time.

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