High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 1/20/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project

This topic outlines the flow for simulating the HBM2 IP instantiated in your project, rather than the HBM2 design example.
  1. In your simulation project, include <project_directory>\<IP_name>\sim\<IP_name>.v
  2. The generated HBM2 IP simulation file set does not include an HBM2 memory model file; you must add a memory model file to the project. Intel® recommends that you use the memory model from the design example simulation file set generated from your IP: hbm_0_example_design\sim\ip\ed_sim\ed_sim_mem\sim\ed_sim_mem.v