6.2.8. Avalon® Memory-Mapped (AVMM) Interface Signals
|ctrl_amm_0_0_waitrequest_n||Output||1||Asserts when HBM is busy.|
|ctrl_amm_0_0_address||Input||28/29||Write or read address, 28-bits wide for 4G device, 29-bits wide for 8-G device.|
|ctrl_amm_0_0_burstcount||Input||7||AVMM burst count, set to 7’h1 for BL4, 7’h2 for burst length 8.|
|ctrl_amm_0_0_byteenable||Input||32||Byte-enable for write data.|
|ctrl_amm_0_0_readdatavalid||Output||1||Asserts when read data is valid.|
|ctrl_ecc_readdataerror_0_0||Output||1||Asserts high by the controller ECC logic to indicate that the read data has an uncorrectable error.|
|ctrl_auto_precharge_0_0||Input||1||Available when the Enable Auto Precharge Control option is selected in Controller Configuration. When asserted high along with a read or write request to the memory controller, indicates that auto-precharge is enabled.|
|ctrl_user_priority_0_0||Input||1||Available when the Enable Command Priority Control option is selected in Controller Configuration. When asserted high along with a read or write request to the memory controller, indicates that the request is high priority and should be fulfilled before other low priority requests.|
For information on using the Avalon® memory-mapped interface, refer to Avalon Interface Specifications.
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