High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 9/27/2021
Public
Document Table of Contents

9. Document Revision History for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.09.27 21.3 19.6.1
  • In the Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel FPGA IP chapter:
    • Updated the FPGA I/O Tab figure in the FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel FPGA IP topic. Also removed the note from beneath the FPGA I/O Tab figure.
    • Added a note to the Address reordering description in the Group: Controller/ Controller 0 Configuration table, in the Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel FPGA IP topic.
  • In the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Interface chapter:
    • Modified the figure in the Clock Signals topic.
    • In the Reset Signals topic, modified text in the hbm_only_reset_in Timing section, and added a waveform to the Reset Recommendations for Reliable Calibration of the HBM2 Interface section.
    • In the AXI User-interface Signals topic, added a note to the AXI Subchannels Descriptions section, and added a note to the axi_0_0_wready description in the User Port 0’s AXI4 Write Data Channel table.
  • In the Simulating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP chapter:
    • Removed ModelSim*- Intel® FPGA Edition reference.
2021.06.21 21.2 19.6.1
  • In the Creating and Parameterizing chapter:
    • Added a paragraph to the Core clock frequency description in Table 8, and added Table 9.
    • Added a note beneath the figure in the FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel FPGA IP topic, and modified the description of Memory PLL Reference clock I/O standard in Table 10.
    • In the Pin Planning for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic, modified the pll_ref_clk description in Table 17.
  • In the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface chapter:
    • Modified the ext_core_clk description in Table 18 in the Clock Signals topic.
    • Added content to the AXI Subchannels Descriptions section in the AXI User-interface Signals topic.
    • Added two notes to the User-controlled Accesses to the HBM2 Controller topic.
2021.03.29 21.1 19.6.1
  • In the Creating and Parameterizing the High Bandwidth Memory chapter, added a sentence to the Core clock frequency description, in the Group: General / Clocks table.
  • In the Simulating the High Bandwidth Memory chapter, removed the Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence NCSim* topic.
  • In the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface chapter:
    • Added one row to the Temperature and Calibration Status Readout topic.
    • Added the Controller Idle State Status topic.
    • Added a sentence to the first paragraph of the Partial Writes section in the ECC Error Correction and Detection topic.
2020.12.14 20.4 19.6.1
  • Added the Register Map IP-XACT Support for HBM2 IP topic to the Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP chapter.
  • Modified the descriptions of axi_0_0_awlen in Table 22, and axi_0_0_arlen in Table 25.
2020.10.05 20.3 19.6.0
  • In the General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic in chapter 4:
    • Modified the figure.
    • Modified the Automatically instantiate backpressure registers within the HBM2 IP entry in Table 6.
  • Added the FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic in chapter 4.
  • In the Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic in chapter 4:
    • Modified the Controller Tab figure.
    • In table 10, modified the Enable AXI Burst length of more than 2 and AXI Maximum burst length descriptions.
  • In the Reset Signals topic in chapter 6:
    • Modified the Reset Signals table.
    • Modified the paragraph under the hbm_only_reset_in Timing heading.
  • In the AXI User-interface Signals topic in chapter 6:
    • Modified the first bullet point in the AXI ID Definition section.
    • Added the AXI Burst Transactions section.
    • Modified the axi_0_0_awid and axi_0_0_awlen descriptions in Table 21.
    • Modified the axi_0_0_arid and axi_0_0_arlen descriptions in Table 24.
  • Removed Non-zero Latency Backpressure topic from chapter 6, and replaced with Improving User Logic to HBM2 Controller AXI Interface Timing.
2020.06.22 20.2 19.5.0
  • In the Introduction chapter, added a new Avalon® interface to the Intel® Stratix® 10 MX HBM2 Controller Features topic.
  • In the Architecture chapter:
    • Added a new Avalon® interface to the Intel® Stratix® 10 MX UIB Architecture topic.
    • Replaced figure 5 and added a new Avalon® interface to the Intel® Stratix® 10 HBM2 Controller Architecture topic.
  • In the Creating and Parameterizing chapter:
    • In the General Parameters topic, modified the description of the Interface Protocol and Enable AXI Switch for channel 0 and 1 parameters in Table 5, and the description of the Allow backpressure of AXI read data and write response channels parameter in Table 6.
    • In the Controller Parameters topic, replaced Figure 8 and modified the following parameter descriptions in Table 9:
      • Interface Protocol
      • Enable Auto Precharge Control
      • Enable Command Priority Control
      • User Read Auto-Precharge Policy
      • User Write Auto-Precharge Policy
      • Data Width per Pseudo-Channel
    • In the Diagnostic Parameters topic, added the new Avalon® interface to several parameter descriptions in Table 10.
    • In the Pin Planning topic, modified the paragraph immediately preceding Table 15.
  • In the IP Interface chapter:
    • Modified the ext_core_clk description in Table 16.
    • Modified the text of the User-interface Signals topic.
    • Added the Avalon® Memory-Mapped (AVMM) Interface Signals topic.
    • In the AXI Switch Selection in HBM2 IP Catalog GUI topic:
      • Added a bullet point to the soft 4×4 AXI switch feature list.
      • Added text to the second bullet point under Arbitration scheme 3: Transaction counts.

Document Version Intel® Quartus® Prime Version IP Version Changes
2020.04.13 20.1 19.4.0
  • In the Creating and Parameterizing chapter, made the following changes to the General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic:
    • Updated the figure for the General tab.
    • Modified the Group: General / HBM2 Interface table.
    • In the Group: General / AXI Interface table, added a paragraph to the Backpressure latency (clock cycles) description.
  • In the Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP chapter:
    • Updated the figure for the Diagnostics tab.
  • In the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface chapter, made the following changes to the AXI User-interface Signals topic:
    • Added the AXI ID Definition section.
    • Added a bullet point and a second figure to the AXI Address Definition section.
    • In the User Port 0’s AXI4 Write Address (Command) Channel table, modified the information for axi_0_0awid and axi_0_0_awaddr.
    • In the User Port 0’s AXI4 Read Address (Command) Channel table, modified the information for axi_0_0arid and axi_0_0_araddr.
  • Updated the AXI Backpressure Latency Selection figure in the Non-zero Latency Backpressure topic.
  • Added the Soft AXI Switch and AXI Switch Selection in HBM2 IP Catalog GUI topics to the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface chapter.
2020.03.02 19.4 19.3.0 In the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface chapter, in the AXI User-Interface Signals topic:
  • Modified the description of the axi_0_0_awsize port in the User Port 0’s AXI4 Write Address (Command) Channel table.
  • In the User Port 0’s AXI4 Write Data Channel table, changed the names and descriptions of the axi_0_0_wuser_data and axi_0_0_wuser_strb ports. Implemented minor changes to the descriptions of the axi_0_0_wstrb and axi_0_0_wvalid ports.
  • Modified the descriptions of the axi_0_0_arsize and axi_0_0_arburst ports in the User Port 0’s AXI4 Read Address (Command) Channel table.
  • Changed the names of the third and fourth entries in the User Port 0’s Read Data Channel table. Added a sentence to the description of the axi_0_0_rvalid port.
2019.12.16 19.4 19.3.0
  • In the Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP chapter:
    • In the General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic, modified the description of the Backpressure latency parameter, in the Group: General / AXI Interface table.
  • In the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface chapter:
    • Added additional information about the hbm_only_reset_in signal, in the Reset Signals topic.
    • Added additional information about clocks and resets in the Reset Signals topic.
    • Retitled the Improving User Logic to HBM2 Controller AXI Interface Timing topic to Non-zero Latency Backpressure. Implemented extensive changes to the topic content.
  • In the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance chapter:
    • Added content about temperature effects, in the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency topic.
2019.09.19 19.2.0 19.2.0
  • In the Introduction to High Bandwidth Memory chapter, clarified description of Pseudo Channel mode in the Intel® Stratix® 10 MX HBM2 Features topic.
  • In the Intel® Stratix® 10 MX HBM2 Architecture chapter, modified the HBM2 DRAM section of the Intel® Stratix® 10 MX UIB Architecture topic.
  • In the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface chapter:
    • Modified the descriptions of the ext_core_clk_locked and in thepll_ref_clk sig in the Clock Signals topic.
    • Modified the descriptions of the axi_0_0_awlen, axi_0_0_awsize, axi_0_0_awburst, axi_0_0_arlen, axi_0_0_arsize, and axi_0_0_arburst ports in the AXI User-interface Signals topic.
    • Minor additions to the AXI Write Address section of the AXI Write Transaction topic, and to the Read Address section of the AXI Read Transaction topic.
2019.07.25 19.2.0 19.2.0
  • Added About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP.
  • Revised the Refresh Mode description in the Group: Controller/ Controller 0 Configuration table in the Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic.
  • Updated Figure 7 in General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP.
  • Updated Figure 9 in Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP.
  • Added row for Disable HBM model transaction messages in simulation to Table 9 in Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP.
  • Updated Figure 13 in Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency.
  • Updated Figure 20 in Improving User Logic to HBM2 Controller AXI Interface Timing.
  • Updated Width values in Tables 23 and 26 in AXI User-interface Signals.
2019.05.03 19.1 19.1
  • Updated image of the Diagnostics tab, in the Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP and the Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency topics.
  • Modified the descriptions of the PLL reference clock frequency description in the Group: General / Clocks table in the General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic
  • Added rows to Group: Diagnostics / Traffic Generator table in the Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic.
  • Added bullet point to the Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency topic.
  • Minor rewording of the third bullet point in the Intel® Stratix® 10 MX HBM2 Controller Features topic.
  • Recast the Jitter Specifications for the Input Reference Clocks section in the Pin Planning for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic.
  • Added content to the Factors Affecting Controller Efficiency section in the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency topic.
  • Added the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives chapter.
2018.12.24 18.1.1 18.1.1
  • Replaced figure 3, Block Diagram of Intel® Stratix® 10 MX HBM2 Implementation in the Intel® Stratix® 10 MX HBM2 Architecture chapter.
  • Reorganized and changed the title of the Generating the Intel® Stratix® 10 MX HBM2 IP chapter to Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP.
  • Removed the Generating the Design Example and High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example topics from the Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP. chapter.
  • Replaced figure 15, HBM2 IP Clocking and Reset Diagram, figure 16, AXI Address Definition, figure 18, AXI Write Transaction, and figure 19, AXI Read Transaction, in the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface chapter.
  • Added the topic Improving User Logic to HBM2 Controller AXI Interface Timing to the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface chapter.
2018.05.07 18.0 18.0
  • Changed document title from Intel® Stratix® 10 MX HBM2 IP User Guide to High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide.
  • Chapter 1, Introduction to High Bandwidth Memory:
    • Added ECC support to Intel® Stratix® 10 MX HBM2 Features topic.
    • Modified fourth and sixth bullets in Intel® Stratix® 10 MX HBM2 Controller Features topic.
  • Chapter 2, Intel® Stratix® 10 MX HBM2 Architecture:
    • Modified both figures in the Intel® Stratix® 10 MX HBM2 Architecture topic.
    • Added sentence to the paragraph immediately before Figure 4, in the Intel® Stratix® 10 MX HBM2 Architecture topic.
    • Expanded the last paragraph in the Intel® Stratix® 10 MX HBM2 Architecture topic.
    • Changed the specified width of write and read data interfaces per AXI port from 128-bits to 256-bits, in the HBM2 burst transactions description in the Intel® Stratix® 10 MX HBM2 Controller Details topic.
    • Removed the last sentence from the User interface vs HBM2 Interface Frequency description, in the Intel® Stratix® 10 MX HBM2 Controller Details topic.
    • Added the ECC description near the end of the Intel® Stratix® 10 MX HBM2 Controller Details topic.
  • Chapter 3, Generating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP:
    • Changed chapter title from Generating the Intel® Stratix® 10 MX HBM2 IP to Generating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP.
    • Changed name of the menu selection in step 3 of the procedure and replaced the figure.
    • Changed the IP name in topic titles throughout the chapter.
    • Changed the description of the Core clock frequency parameter in the Group: General / Clocks section of the General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic.
    • In the Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP topic, removed two existing graphics and added one new one. Added Enable mixed traffic parameter to the Group: Diagnostics / Traffic Generator section.
    • Revised the procedure in the Generating the Example Design topic.
    • Removed the Intel® Stratix® 10 MX HBM2 IP Example Design for Synthesis topic.
    • Added the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example and High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Pin Planning topics.
    • In the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Pin Planning topic, changed Jitter Specifications for the Input Reference Clocks from 10ps peak-to-peak to 20ps peak-to-peak.
  • Chapter 4, Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP:
    • Changed product name from Intel® Stratix® 10 MX HBM2 IP to High Bandwidth Memory (HBM2) Interface Intel® FPGA IP in topic titles throughout the chapter.
  • Chapter 5, High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface:
    • Changed product name from Intel® Stratix® 10 MX HBM2 IP to High Bandwidth Memory (HBM2) Interface Intel® FPGA IP in topic titles throughout the chapter.
    • Revised content of Clock Signals and Reset Signals topics.
    • Added Calibration Status Signals and Memory Interface Signals topics.
    • Added AXI Interface Signals and AXI Address Definition sections to the AXI User-interface Signals topic. Removed content from the descriptions of the axi_0_0_awaddr and axi_0_0_araddr ports, in tables 15 and 18, respectively.
    • Added User APB Interface Timing and User-controlled Access to the HBM2 Controller topics.
    • Added figures to the User Refresh Per Bank and User Refresh to All Banks sections in the User-controlled Refreshes topic.
  • Chapter 6,High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance:
    • Changed chapter title from Intel® Stratix® 10 MX HBM2 IP Controller Performance to High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance.
    • Changed the IP name in topic titles throughout the chapter.
    • Added High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout topic.
Date Version Changes
December 2017 2017.12.22 Initial public release.

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