High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 1/20/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2.1. Clock Signals

Figure 16. HBM2 IP Clocking and Reset Diagram
Table 18.  Clock Signals
Signal Direction Description
ext_core_clk Input Core clock. Output of user-instantiated I/O PLL. The HBM2 IP does not instantiate the I/O PLL required to generate the ext_core_clk.

When the core clock frequency is one-half of the HBM2 interface frequency, the reference clock that drives the core I/O PLL must come from the same oscillator as that supplying the UIB PLL reference clock on the board for a given HBM2 interface. Failure to follow this guideline can result in calibration not completing successfully or the AXI bus locking up.

Although you can set the core clock frequency to a maximum of one-half of the memory clock, Intel® recommends not exceeding the recommended core clock limits presented in Table 9 to avoid potential timing closure problems.

ext_core_clk_locked Input LOCKED status of I/O PLL driving ext_core_clk, indicating the ext_core_clk is stable. This I/O PLL should achieve LOCKED status within 1ms of device configuration for calibration to be successful. The I/O PLL driving the ext_core_clk cannot be reset after calibration is completed.
pll_ref_clk Input LVDS reference clock input for UIB PLL. This reference clock must be provided through dedicated UIB_PLL_REF_CLK_p/n pins available in Intel® Stratix® 10 devices and cannot be provided through an internal I/O PLL. The pll_ref_clk must be stable and free-running at device power-up for successful configuration. Refer to Intel® Stratix® 10 pin connection guidelines for information on how to supply these clocks.
wmc_clk_x_clk Output

Core clock output feedback from UIB, based on ext_core_clk provided, one per HBM2 Channel (represented by x).

Intel® recommends that the user interface drive the AXI interface for the corresponding channels with this clock.

phy_clk_x_clk Output UIB PHY clk output. Not supported. Leave unconnected. This signal appears as phy_clk_x conduit in the Platform Designer.

Clocking recommendations for Reliable Calibration of the HBM2 Interface

Observe the following clock guidelines for reliable calibration of the HBM2 interface:

  • The UIB PLL reference clocks (one per HBM2 interface) must be provided through an external clock source and must be stable and free running prior to configuration and stable thereafter.
  • The I/O PLL driving the core clock (ext_core_clk) should achieve a LOCKED condition within one millisecond of device configuration. This I/O PLL cannot be reset once the interface is calibrated.
  • For a given HBM2 interface, Intel® recommends that the same clock source provide the reference clocks for both the I/O PLL and the UIB PLL.