- 4.1. Creating an Intel® Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2) Interface FPGA IP
- 5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator
7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing
For the best HBM2 efficiency, ensure that your user logic follows best design practices. Take care to avoid combinatorial paths between the AXI master and slave input and output signals. Add pipeline registers as necessary and reduce logic levels in timing-critical paths to successfully meet core timing requirements. The Backpressure Latency feature allows you to add up to two register stages between the user interface and the HBM2 IP. Refer to Improving User Logic to HBM2 Controller AXI Interface Timing for details on Backpressure Latency.
The following documents provide detailed information on the Intel® Stratix® 10 device architecture and design techniques that you can adopt to achieve the best core performance:
- The Intel® Stratix® 10 High Performance Design Handbook.
- The Timing Closure and Optimizations chapter of the Design Optimization User Guide: Intel® Quartus® Prime Pro Edition .
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