3.3. Intel® Stratix® 10 HBM2 Controller Architecture
Each controller consists of a write and read data path and the control logic that helps to translate user commands to the HBM2 memory. The HBM2 controller logic accounts for the HBM2 memory specification timing and schedules commands in an efficient manner. The following figure shows a block diagram of the HBM2 controller, corresponding to channel 0. The HBM2 controller's user-logic interface follows the AXI interface as well as the Avalon® memory-mapped interface (commencing in the Intel® Quartus® Prime software version 20.2. You can find more information about the interface timing details in the User AXI Interface Timing section.
Did you find the information on this page useful?