High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

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ID 683189
Date 1/20/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 2. Introduction to High Bandwidth Memory 3. Intel® Stratix® 10 HBM2 Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface 7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance 8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives 9. Document Revision History for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2 in Intel® Stratix® 10 Devices 2.2. HBM2 DRAM Structure 2.3. Intel® Stratix® 10 HBM2 Features 2.4. Intel® Stratix® 10 HBM2 Controller Features
3. Intel® Stratix® 10 HBM2 Architecture x
3.1. Intel® Stratix® 10 HBM2 Introduction 3.2. Intel® Stratix® 10 UIB Architecture 3.3. Intel® Stratix® 10 HBM2 Controller Architecture
3.3. Intel® Stratix® 10 HBM2 Controller Architecture x
3.3.1. Intel® Stratix® 10 HBM2 Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
4.1. Creating an Intel® Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.3. Pin Planning for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.4. Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.6. Register Map IP-XACT Support for HBM2 IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design 5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa* 5.3. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Synopsys VCS* 5.4. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Riviera-PRO* 5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator 5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency 5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface x
6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram 6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals 6.3. User AXI Interface Timing 6.4. User APB Interface Timing 6.5. User-controlled Accesses to the HBM2 Controller 6.6. Soft AXI Switch
6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals x
6.2.1. Clock Signals 6.2.2. Reset Signals 6.2.3. Calibration Status Signals 6.2.4. Memory Interface Signals 6.2.5. User-interface Signals 6.2.6. AXI User-interface Signals 6.2.7. Sideband APB Interface 6.2.8. Avalon® Memory-Mapped (AVMM) Interface Signals
6.3. User AXI Interface Timing x
6.3.1. AXI Write Transaction 6.3.2. AXI Read Transaction 6.3.3. Improving User Logic to HBM2 Controller AXI Interface Timing
6.4. User APB Interface Timing x
6.4.1. Advanced Peripheral Bus Protocol 6.4.2. APB Interface Timing
6.5. User-controlled Accesses to the HBM2 Controller x
6.5.1. User-controlled Refreshes User Refresh Per Bank User Refresh to All Banks Self Refresh 6.5.2. Temperature and Calibration Status Readout 6.5.3. Controller Idle State Status 6.5.4. Power Down Status 6.5.5. ECC Error Status 6.5.6. User Interrupt 6.5.7. ECC Error Correction and Detection
6.5.6. User Interrupt x
6.5.6.1. Interrupt Enable and Conditions for Interrupt Generation 6.5.6.2. Interrupt Status 6.5.6.3. Error Valid Status
6.6. Soft AXI Switch x
6.6.1. AXI Switch Selection in HBM2 IP Catalog GUI
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance x
7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth 7.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency 7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency 7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing 7.5. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. Introduction to High Bandwidth Memory
3. Intel® Stratix® 10 HBM2 Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance
8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives
9. Document Revision History for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

6.5.1. User-controlled Refreshes

By default, the HBM2 parameter editor settings allow the HBM2 controller to schedule Refresh commands to the HBM2 DRAM. However, user logic can also issue Refresh commands to memory.

If you want to allow user logic to issue Refresh requests, you must specify so in the Controller Settings of the parameter editor, as follows:

Change the Controller Settings > REFRESH MODE value from Controller Refresh All to User Refresh All or User Refresh Per-bank.

Each APB interface corresponds to one HBM2 channel, therefore requests must be addressed to either of the two Pseudo Channels, one Pseudo Channel at a time.

The timing of the refresh interval is specific to the HBM2 DRAM timing. The required refresh rate is provided by the HBM2 DRAM through the TEMP[2:0] vector, which can be read through the APB interface.

Table 29.  DRAM Refresh Timing
TEMP[2:0] Refresh Rate
000 4x tREFI
001 2x tREFI
011 1x tREFI
010 0.5x tREFI
110 0.25x tREFI
111 TBD
101 TBD
100 TBD

Refresh command options available from user logic are as follows:

  • User refresh commands issued on a per bank basis. This corresponds to banks corresponding to the HBM2 Pseudo Channel.
  • User refresh commands to all banks. This corresponds to all banks corresponding to the HBM2 Pseudo Channel.
  • Self-refresh command.

All the user refresh requests follow the APB interface protocol. User logic issues the Refresh request and waits for the acknowledgement signal from the HBM2 controller before issuing another Refresh request.

User Refresh Per Bank

User refresh requests per-bank consist of the following commands issued to the APB Interface

Table 30.  APB Write Data Definition for User Refresh Request Per Bank
Write Data Definition for Refresh Request Description
[0] Pseudo Channel Number. Set the following values to indicate the Pseudo channel number:

0 - Pseudo Channel 0

1 - Pseudo Channel 1
[5:1]

Bank number for per-bank refresh.

Bit[5] - Stack ID in 8GB configuration.

Bit[4:1] – 4-bit Bank Address.
[6] Select Per bank or all bank refresh. Set to 1’b0 for per bank refresh.
[7] Reserved. Set to 1'b0.
[8] User initiated refresh request. Set this bit to 1’b1 to initiate refresh command.
[12:10] Number of bursts for per bank refresh bursting feature. Burst = value[1:0] + 1. The per-bank refresh bursting is a feature supported by the HBM2 controller where the user interface can request refresh commands to be issued to more than one HBM2 DRAM bank.
[15:13] Increment value for per bank refresh bursting feature; rolls over once it reached the max bank value. Increment = value[2:0] + 1, where value refers to the current bank address when the write command is issued. This becomes the starting bank address.
Note: The ratio of maximum increment value to total number of banks per Pseudo Channel divided by 4. (For example, a 4H device has a maximum value of 16/4=4.)

To issue user refresh commands on a per-bank basis, follow these steps:

  1. Write to address 16’h0000 with corresponding Write Data.
    • For example, Write data of 16’b0000_0001_0000_0010 (Pseudo-channel 0; bank address is located in Bits[5:1] ; Bit[6] set to 0 for per-bank refresh; Bit [8] set to User initiated Refresh Request).
    • To issue multiple burst of per-bank refresh, set corresponding bits in PWDATA[12:10] and PWDATA[15:13] with desired settings.
  2. Read from address 16’h0000 for Refresh Request Acknowledge.
  3. Wait till PRDATA[9] returns 1’b1 to indicate refresh request is accepted by controller. You can ignore the values of all the other bits of PRDATA. The following figure explains the timing of per-bank refresh request to the APB Interface.
    Figure 30. Timing of APB Refresh Request Per Bank

Individual requests to different Pseudo Channels must be issued serially. You must wait for the HBM2 controller to issue the Acknowledge signal before issuing another Refresh request.

User Refresh to All Banks

Table 31.  APB Write Data Definition for User Refresh Request to All Banks
Write Data Bit Definition for Refresh Request Description
[0] Pseudo Channel Number. Set a value of 0 for Pseudo Channel 0, or a value of 1 for Pseudo Channel 1.
[5:1] Bank number for per-bank refresh. Ignored for All bank refresh.
[6] Select Per bank or all bank refresh. Set to 1’b1 - all banks refresh.
[7] Reserved. Set to 1'b0.
[8] User initiated refresh request. Set this bit to 1’b1 to initiate refresh command.
[15:9] Ignored.
Table 32.  APB Read Data Definition for User Refresh Request
Read Data Bit Definition for Refresh Request Description
[8:0] Reserved.
[9] HBM2 controller-issued Refresh Request Acknowledge.
  • 1'b1 – Read data of 1’b1 indicates that the HBM2 controller Acknowledge of Refresh command.
  • Once a refresh request has been issued, you must wait for the Acknowledge bit to be asserted before issuing further requests.
[15:10] Reserved.

To issue user refresh commands to all banks, follow these steps:

  1. Write to address 16’h0000 with corresponding Write Data.
    • For example, Write data of 16’b0000_0001_0100_0010 (Pseudo Channel 0; bank address is located in Bits[5:1] ; Bit[6] set to 1 for all-banks refresh; Bit [8] set to User initiated Refresh Request).
  2. Read to Address 16’h0000 for Refresh Request Acknowledge.
  3. Wait till PRDATA[9] returns a value of 1’b1 to indicate User Refresh request is accepted by the controller. The following figure explains the APB interface timing for refresh request to all banks.
    Figure 31. Timing of APB Refresh Request to All Banks

Self Refresh

To enter a Self Refresh state, issue these commands to the APB interface:

  1. Write to address 16’h004 with Write Data(PWDATA) of 16’h0001.
  2. Read from address 16’h004. Wait until Read Data (PRDATA [1]) returns a value of 1’b1 to indicate that the HBM2 controller is in a Self Refresh state.

To exit a Self Refresh state, issue this command to the APB interface:

  • Write to address 16’h0004 with Write Data(PWDATA) of 16’h0000 to exit Self-Refresh. Wait for the Self Refresh Acknowledge to be 1’b0 prior to issuing another Self Refresh request.

The write data bus is used to request entry or exit from self refresh. The Read data bus is used to read the self-refresh status of the HBM2 channel. The following tables provide the Write and Read data definitions for accessing self refresh.

Table 33.  APB Write Data Bit Definition for Self Refresh
Write Data Bit Definition Description
[0] User-initiated Self-Refresh Request. To enter Self Refresh:
  • 1’b1: to enter Self Refresh.
  • When asserted, indicates Self Refresh request. Set this bit to 1’b1 to initiate entry to Self Refresh.
To exit Self Refresh:
  • 1’b0: to exit Self Refresh.
  • Clear this bit to 1’b0 to exit Self Refresh.
[15:1] Reserved.
Table 34.  APB Read Data Bit Definition for Self Refresh
Read Data Bit Definition Description
[0] Reserved.
[1] Self refresh status:
  • 1’b1 – HBM Channel is in Self Refresh.
  • 1’b0 – HBM Channel is not in Self Refresh.
[15:2] Reserved.
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