High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 9/27/2021
Public
Document Table of Contents

6.4. User APB Interface Timing

The Advanced Peripheral Bus (APB) interface lets you issue user-controlled refresh signals and access the HBM2 controller’s Control and Status registers.

Unlike the AXI4 interface which provides for high-bandwidth, main band operations and where each HBM pseudo-channel maps to its own dedicated AXI4 port, the APB interface provides for relatively low-bandwidth sideband operations. (For example, to provide an alternative means of controlling refreshes without colliding with the main traffic stream, and for issuing custom commands useful for debugging.) Another difference is that the APB bus interface commands can target one or both Pseudo Channels at the same time, as there is one APB interface per HBM2 channel or two HBM2 Pseudo Channels.

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