High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 9/27/2021
Public
Document Table of Contents

6.5.6.1. Interrupt Enable and Conditions for Interrupt Generation

If you want interrupts to occur based on certain conditions, you must set the conditions to enable interrupt generation.

To enable interrupt generation, issue a Write command to address location 16’h0100 (for Pseudo Channel 0) and 16’h0200 (for Pseudo Channel 1), with the corresponding Write Data (PWDATA).

  • PWDATA[0] – Interrupt enable.
  • PWDATA[11:1] - Lists the various status signals that you can use, alone or in combination, to trigger the Interrupt signal.
    • Set the Mask value to 1’b0 to use the corresponding error condition to generate the Interrupt signal.
    • If you set the Mask value to 1’b1, the Interrupt generator ignores that specific error condition. For example, to use the double-bit error condition to generate the Interrupt signal, set PWDATA[2] to 1’b0.

The following table describes the 16-bit Write Data (PWDATA) for setting the Interrupt Enable, and the conditions of the interrupt.

Table 39.  Interrupt Conditions
Write Data Bit Definition Description
[0] Interrupt Enable: Enables interrupt to the HBM2 controller when the conditions set in PWDATA[11:1] are TRUE.

1 – Enable Interrupt

0 – Disable Interrupt

[1] SBE Interrupt Mask.
[2] DBE Interrupt Mask.
[3] Read DPE Interrupt Mask.
[4] Write DPE Interrupt Mask.
[5] Address Command Interrupt Mask.
[6] CATTRIP Interrupt Mask.
[7] Calibration Interrupt Mask.
[8] Write SRAM SBE Interrupt Mask.
[9] Write SRAM DBE Interrupt Mask.
[10] Read SRAM SBE Interrupt Mask.
[11] Read SRAM DBE Interrupt Mask.
[15:12] Reserved.

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