High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

ID 683189
Date 9/27/2021
Public
Document Table of Contents

6.2.4. Memory Interface Signals

The following HBM2 memory signals are driven by the HBM2 controller through the UIBSS; you do not need to drive these signals.. These signals are provided at the top level, for successful compilation.
Table 21.  HBM2 Memory Interface Signals
Signal Direction Width Description
Cattrip Input 1

HBM2 signals common to each HBM2 interface; these signals must be brought out to the design top level. You do not need to drive these signals and can leave them unconnected.

These signals are grouped under a conduit named m2u_bridge in the Platform Designer, and must be exported.

Temp Input 3
Wso Input 8
Reset_n Output 1
Wrst_n Output 1
Wrck Output 1
Shiftwr Output 1
Capturewr Output 1
Selectwir Output 1
Wsi Output 1
Ck_t Output 1

HBM2 signals per HBM2 channel. You do not need to drive these signals and can leave them unconnected.

These signals are grouped under a conduit named mem_x in the Platform Designer. You should leave this conduit unconnected and ignore any warning message about mem_x being unconnected.

Ck_c Output 1
Cke Output 1
C Output 8
R Output 6
Dq Inout 128
Dm Inout 16
Dbi Inout 16
Par Inout 4
Derr Inout 4
Rdqs_t Input 4
Rdqs_c Input 4
Wdqs_t Output 4
Wdqs_c Output 4
Rd Inout 8
Rr Output 1
Rc Output 1
Aerr Input 1

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