High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

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ID 683189
Date 9/27/2021
Public
Document Table of Contents

5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency

The default traffic pattern can achieve high efficiency by efficiently utilizing the HBM2 memory bandwidth and providing an efficient flow of traffic between the HBM2 controller and AXI user interface.

The main steps to deriving higher efficiency are:

  • Turn off Enable Reorder Buffer on the Controller tab. The Reorder Buffer rearranges the read data in the order of the issued requests.
  • Turn on Force traffic generator to issue different AXI Read/Write IDs and Enable Efficiency Test Mode on the Diagnostics tab. In this configuration, the traffic generator issues concurrent read and write transactions; consequently, you may receive data mismatch warnings, which you can ignore.
  • Turn on Use efficiency pattern and Enable data check for efficiency measurement on the Diagnostics tab, to have the traffic generator use an efficiency pattern to test both synthesis and simulation designs. Ensure that the Read count and Write count values are equal, for the validity check to pass. For best HBM2 efficiency, select a Sequence value of Sequential.

The following sections explain the General, Controller, and Diagnostic tab parameters required to perform high efficiency HBM2 simulation. The following figures illustrate parameter settings for a high-efficiency simulation for a single-channel HBM2 controller.

For more information about improving controller efficiency, refer to High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance.

Figure 13. Controller Tab Settings for High Efficiency Simulation
Figure 14. Diagnostics Tab Settings for High Efficiency Simulation

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