4.3. Pin Planning for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
- UIB PLL reference clock – Reference clock input for the UIB PLL. There is one UIB PLL reference clock per HBM2 interface.
- Core clock input – Fabric core clock, generated through an I/O PLL.
When the core clock frequency is one-half of the HBM2 clock frequency, the reference clock that drives the core I/O PLL should come from the same oscillator as that supplying the UIB PLL reference clock on the board for a given HBM2 interface.
|Signal||Description||Pin Placement Guidelines|
The HBM2 IP parameter editor allows the selection of the following I/O standards:
Refer to the Intel® Stratix® 10 General Purpose I/O User Guide and Intel® Stratix® 10 Pin Connection Guidelines for termination recommendations based on the I/O standard chosen for the UIB PLL reference clock.
|Place this reference clock input on the UIB_PLL_REF_CLK_00 pins while using the HBM2 device on the bottom of the FPGA, or the UIB_PLL_REF_CLK_01 pins while using the HBM2 on the top of the FPGA.|
|ext_core_clk||LVDS differential input clock for generating the fabric core clock. Instantiate the I/O PLL that generates the core clock for the HBM2 IP.||Place the reference clock input on CLK_ pins to access the I/O PLL. You should select pins that are close to the UIB_PLL_REF_CLK input. You must instantiate the I/O PLL in the design flow. The output of the I/O PLL serves as the EXT_CORE_CLK.|
Jitter Specifications for the Input Reference Clocks
Both the reference clock inputs should meet and not exceed the following time interval error (TIE) jitter requirements:
- 20ps peak-to-peak
- 1.42ps RMS at 1e-12 BER
- 1.22ps at 1e-16 BER
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