JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents Test Pattern Checker

The test pattern checker is implemented in the top level RTL file, not in the Platform Designer (Standard) project. The test pattern checker checks one of three patterns; parallel PRBS, alternate checkerboard, or ramp wave from the transport layer during test mode. The test pattern checker has many customization options and you may modify the test pattern checker RTL to customize it to your specifications. Furthermore, for certain parameters like M, S, N, and test mode, the test pattern checker shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core affects the test pattern generator in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR. By default, the software does not contain any dynamic reconfiguration features but you can use the Platform Designer (Standard) system to implement such feature in the software.