JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Public

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1.7.4. Nios II Processor Design Example System Parameters

The top level HDL file (jesd204b_ed.sv) includes system parameters that define the configuration of the example design as a whole. You can change the values in the HDL file after generation to customize to your desired configuration but the values must fall within the supported value ranges.

Table 42.  System Parameter
Parameter Value 19 Description
LINK 1, 2 Number of JESD204B link. One link represent one JESD204B instance.
L 1, 2, 4, 8 Number of lanes per converter device.
M 1, 2, 4, 8 Number of converters per device.
F 1, 2, 4, 8 Number of octets per frame.
S 1, 2 Number of transmitted samples per converter per frame.
N 12–16 Number of conversion bits per converter.
N' 16 Number of transmitted bits per sample.
CS 0–3 Number of JESD204B control bits per conversion sample.
F1_FRAMECLK_DIV 1, 4 The divider ratio for frame_clk when F = 1 (refer to Core PLL section.
F2_FRAMECLK_DIV 1, 2 The divider ratio for frame_clk when F = 2 (refer to Core PLL section..
POLYNOMIAL_LENGTH 7, 9, 15, 23, 31 Defines the polynomial length for the PRBS pattern generator and checker, which is also the equivalent number of stages for the shift register.
  • If PRBS-7 is required, set this parameter to 7.
  • If PRBS-9 is required, set this parameter to 9.
  • If PRBS-15 is required, set this parameter to 15.
  • If PRBS-23 is required, set this parameter to 23.
  • If PRBS-31 is required, set this parameter to 31.
This parameter value must not be larger than N, which is the output data width of the PRBS pattern generator or converter resolution. If an N of 12-14 is required, PRBS-7 and PRBS-9 are the only feasible options. If an N of 15-16 is required, PRBS-7, PRBS-9, and PRBS-15 are the only feasible options.
FEEDBACK_TAP 6, 5, 14, 18, 28 Defines the feedback tap for the PRBS pattern generator and checker. This is an intermediate stage that is XOR-ed with the last stage to generate to next PRBS bit.
  • If PRBS-7 is required, set this parameter to 6.
  • If PRBS-9 is required, set this parameter to 5.
  • If PRBS-15 is required, set this parameter to 14.
  • If PRBS-23 is required, set this parameter to 18.
  • If PRBS-31 is required, set this parameter to 28.
19 Values supported or demonstrated by this design example.