JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents

1.7.8. Running the Software Control Flow

The key feature of the design example with Nios II processor control unit is the ability to control certain aspects of JESD204B system using a C-based, software control flow.

The software control flow allows you to perform the following tasks:

  • System reset – ability to reset individual modules (core PLL, transceiver PHY, JESD204B base Avalon-MM interface, link clock domain, and frame clock domain) independently or in sequence.
  • Initial and dynamic, real-time configuration of external converter devices via SPI interface.
  • Dynamic reconfiguration of key modules in the design example subsystem (for example, JESD204B IP core base layer, transceiver PHY, core PLL).
  • Error handling via interrupt service routines (ISR).
  • Status register readback.
  • Dynamic switching between real-time operation and test mode.

The software C code included as part of the design example only performs basic JESD204B link initialization. You can modify the code to perform some or all of the tasks above as per your system specifications.

Figure 29. Software C Code Execution FlowFigure illustrates the main C code execution flow

The JESD204B link initialization performs the following tasks:

  • Set the pattern type or user mode for the pattern generator or checker. The default pattern type is set to PRBS.
  • Set the loopback mode. The default is internal serial loopback mode.
  • Pulse SYSREF (required to meet Subclass 1 requirements)
  • Wait 10 seconds to allow for changes to take effect.
  • Report the link status.