JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents PLL Reconfiguration

The PLL reconfiguration utilizes the ALTERA_PLL_RECONFIG IP core to implement reconfiguration logic to facilitate dynamic real-time reconfiguration of PLLs in Intel® FPGA devices. You can use this megafunction IP core to update the output clock frequency, PLL bandwidth, and phase shifts in real time, without reconfiguring the entire FPGA.

The design example uses the MIF approach to reconfigure the core PLL. The ALTERA_PLL_RECONFIG IP core has two parameter options—Enable MIF Streaming and Path to MIF file—for the MIF input. Turn on Enable MIF Streaming option and set the core_pll.mif as the value to Path to MIF file parameter.

The following PLL reconfiguration Avalon-MM operations occurs during data rate reconfiguration.

Table 9.  PLL Reconfiguration Operation
Operation Avalon-MM Interface Signal Byte Address Offset (6bits) Bit Value
Arria V and Stratix V Devices
Set MIF base address pll_mgmt_* 0x01F [8:0] 0x000 (maximum configuration) or

0x02E (downscale configuration)

Write to the START register to begin pll_mgmt_* 0x02 [0:0] 0x01
Arria 10 Devices
Start MIF streaming with MIF base address specified in data value pll_mgmt_* 0x010 [31:0] 0x000 (maximum configuration) or

0x02E (downscale configuration) 7

7 The MIF base address is 9 bits (LSB). The remaining bits are reserved.