JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents Hardware Setup

The Arria 10 GX FPGA development board with a 10AX115 device features two FPGA mezzanine card (FMC) connectors for you to interoperate with external converters.

Figure 28. Block Diagram of the JESD204B Reference Design with Nios II Processor

This figure illustrates the example design block diagram implemented on the Arria 10 GX FPGA development board.

The JESD204B serial data, control, and configuration signal pins are assigned to FMC port A connector. To interoperate with your converter device, ensure that the pin assignments for the JESD204B serial data, control, and configuration ports are set correctly according your converter specifications. The global reset pin (global_rst_n) connects to the user PB0 push-button on the board. The control plane clock (mgmt_clk) is sourced from the on-board Si570 programmable oscillator. The Si570 clock output routes through a Si53301 clock buffer that allows you to select between the Si570 clock output and SMA input. Follow the instructions in the Programming the Device section to set the board settings correctly.

The example design is configured in internal serial loopback mode. Therefore, the JESD204B data path reference clock (device_clk) is sourced from an on-board clock source, the Si5338 programmable oscillator. In general, when interoperating with an external converter, the device_clk is sourced from the converter through the FMC connector. If this suits your configuration, modify the device_clk pin assignments accordingly to assign the pin to the FMC connector.