JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

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Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with NIOS Control Unit 1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with NIOS Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Platform Designer (Standard) System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Platform Designer (Standard) System Component x
1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard) 1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard) 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Platform Designer (Standard) Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B Intel® FPGA IP Design Example User Guide

1.6.2. System Parameters

Table 30.  System Parameter SettingsThis table lists the parameters exposed at the system level.
Parameter Value 16 Default Description
LINK 1, 2 1 Number of JESD204B link. One link represent one JESD204B instance.
L 1, 2, 4, 8 2 Number of lanes per converter device.
M 1, 2, 4, 8 2 Number of converters per device.
F 1, 2, 4, 8 2 Number of octets per frame.
S 1, 2 1 Number of transmitted samples per converter per frame.
N 12–16 16 Number of conversion bits per converter.
N' 16 16 Number of transmitted bits per sample in the user data format.
F1_FRAMECLK_DIV 1, 4 4 The divider ratio on frame_clk when F = 1. The transport layer uses the post-divided frame_clk.
F2_FRAMECLK_DIV 1, 2 2 The divider ratio on frame_clk when F = 2. The transport layer uses the post-divided frame_clk.
POLYNOMIAL_LENGTH 7, 9, 15, 23, 31 7 Defines the polynomial length for the PRBS pattern generator and checker, which is also the equivalent number of stages for the shift register.
  • If PRBS-7 is required, set this parameter to 7.
  • If PRBS-9 is required, set this parameter to 9.
  • If PRBS-15 is required, set this parameter to 15.
  • If PRBS-23 is required, set this parameter to 23.
  • If PRBS-31 is required, set this parameter to 31.
This parameter value must not be larger than N, which is the output data width of the PRBS pattern generator or converter resolution. If an N of 12-14 is required, PRBS-7 and PRBS-9 are the only feasible options. If an N of 15-16 is required, PRBS-7, PRBS-9, and PRBS-15 are the only feasible options.
FEEDBACK_TAP 6, 5, 14, 18, 28 6 Defines the feedback tap for the PRBS pattern generator and checker. This is an intermediate stage that is XOR-ed with the last stage to generate to next PRBS bit.
  • If PRBS-7 is required, set this parameter to 6.
  • If PRBS-9 is required, set this parameter to 5.
  • If PRBS-15 is required, set this parameter to 14.
  • If PRBS-23 is required, set this parameter to 18.
  • If PRBS-31 is required, set this parameter to 28.

The table below lists the configuration that this design example supports. However, the design example generated by the Platform Designer (Standard) system is always fixed at a data rate of 6144 Mbps and a limited set of configuration as shown in the table below. If your setting in the Platform Designer (Standard) parameter editor does not match one of the LMF and bonded mode parameter values in the following table, the design example is generated with the default values of LMF = 124.

Table 31.  Static and Dynamic Reconfiguration Parameter Values Supported
Mode Link L M F Reference Clock Frame Clock Link Clock F1_FRAMECLK_DIV F2_FRAMECLK_DIV
Static
Bonded/Non-bonded 1 1 1 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 1 1 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 1 2 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 1 2 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 1 4 8 153.6 76.8 153.6 1
Bonded/Non-bonded 1 2 1 1 153.6 153.6 153.6 4
Bonded/Non-bonded 1 2 1 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 2 1 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 2 1 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 2 2 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 2 2 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 2 4 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 2 4 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 2 8 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 4 1 1 153.6 153.6 153.6 4  
Bonded/Non-bonded 1 4 1 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 4 1 4 153.6 153.6 153.6 1  
Bonded/Non-bonded 1 4 2 1 153.6 153.6 153.6 4
Bonded/Non-bonded 1 4 2 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 4 2 4 153.6 153.6 153.6 1  
Bonded/Non-bonded 1 4 2 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 4 4 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 4 4 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 4 4 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 4 8 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 4 8 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 4 16 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 8 1 1 307.2 153.6 153.6 4
Bonded/Non-bonded 1 8 1 2 307.2 153.6 153.6 2
Bonded/Non-bonded 1 8 2 1 307.2 153.6 153.6 4
Bonded/Non-bonded 1 8 2 2 307.2 153.6 153.6 2
Bonded/Non-bonded 1 8 2 4 307.2 153.6 153.6 1  
Bonded/Non-bonded 1 8 4 1 307.2 153.6 153.6 4
Bonded/Non-bonded 1 8 4 2 307.2 153.6 153.6 2
Bonded/Non-bonded 1 8 4 4 307.2 153.6 153.6 1  
Bonded/Non-bonded 1 8 4 8 307.2 76.8 153.6 1  
Bonded/Non-bonded 1 8 8 2 307.2 153.6 153.6 2
Bonded/Non-bonded 1 8 8 4 307.2 153.6 153.6 1  
Bonded/Non-bonded 1 8 8 8 307.2 76.8 153.6 1  
Bonded/Non-bonded 1 8 16 4 307.2 153.6 153.6 1  
Bonded/Non-bonded 1 8 16 8 307.2 76.8 153.6 1  
Bonded/Non-bonded 1 8 32 8 307.2 76.8 153.6 1
Bonded/Non-bonded 2 1 1 2 153.6 153.6 153.6 2
Bonded/Non-bonded 2 2 2 2 153.6 153.6 153.6 2
Dynamic Reconfiguration
Non-bonded 2 2 2 2 153.6 153.6 153.6 2
The following figures show the datapath of single and multiple JESD204B links.
Figure 20.  Datapath of A Single JESD204B Link


Figure 21.  Datapath of Multiple JESD204B Links



Section Content
Run-Time Reconfiguration

16 Values supported or demonstrated by this design example.
Level Two Title