JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

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ID 683094
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with NIOS Control Unit 1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with NIOS Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Platform Designer (Standard) System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Platform Designer (Standard) System Component x
1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard) 1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard) 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Platform Designer (Standard) Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B Intel® FPGA IP Design Example User Guide

1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard)

The Nios II subsystem Platform Designer (Standard) project, nios_subsystem.qsys 18, instantiates the following peripherals:

  • Nios II processor (altera_nios2_gen2)
  • On-chip memory (altera_avalon_onchip_memory2)—provides both instruction and data memory space
  • Timer (altera_avalon_timer)—provides a general timer function for the software
  • JTAG UART (altera_avalon_jtag_uart)—serves as the main communications portal between the user and the Nios II processor via the terminal console in Nios II SBT for Eclipse tool
  • Avalon-MM bridges (altera_avalon_mm_bridge)—two Avalon-MM bridge modules; one to interface to the JESD204B subsystem and the other to interface to the Platform Designer (Standard) components (core PLL reconfiguration controller and SPI master modules) in the top level Platform Designer (Standard) project.
  • PIO (altera_avalon_pio)—provides general input/output (I/O) access from the Nios II processor to the HDL components in the FPGA via two sets of 32-bit registers:
    • io_status—status registers input from the HDL components to the Nios II processor
    • io_control—control registers output from the Nios II processor to the HDL components

The tables below describe the signal connectivity for the io_status and io_control registers.

Table 36.   Signal Connectivity for io_status Registers
Bit Signal
0 Core PLL locked
1 TX transceiver ready (Link 0)
2 RX transceiver ready (Link 0)
3 Test pattern checker data error (Link 0)
4–31 TX transceiver ready, RX transceiver ready, and test pattern checker data error signals for subsequent links, if present.
Table 37.   Signal Connectivity for io_control Registers
Bit Signal
0 RX serial loopback enable for lane 0 (Link 0)
1 RX serial loopback enable for lane 1 (Link 0)
2 RX serial loopback enable for lane 2 (Link 0)
3 RX serial loopback enable for lane 3 (Link 0)
4–30 RX serial loopback enable for subsequent links, if present.
31 Sysref (Not implemented in software)

You can access the address map of the submodules in the Nios II subsystem by clicking on the Address Map tab in the Platform Designer (Standard) window.

18 Note that Platform Designer (Standard) does not allow multiple Platform Designer (Standard) systems with the same name in the same project. If you have a Platform Designer (Standard) system with the same name, please change the name of your Platform Designer (Standard) system.
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