JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents Nios II Subsystem in Platform Designer (Standard)

The Nios II subsystem Platform Designer (Standard) project, nios_subsystem.qsys 18, instantiates the following peripherals:

  • Nios II processor (altera_nios2_gen2)
  • On-chip memory (altera_avalon_onchip_memory2)—provides both instruction and data memory space
  • Timer (altera_avalon_timer)—provides a general timer function for the software
  • JTAG UART (altera_avalon_jtag_uart)—serves as the main communications portal between the user and the Nios II processor via the terminal console in Nios II SBT for Eclipse tool
  • Avalon-MM bridges (altera_avalon_mm_bridge)—two Avalon-MM bridge modules; one to interface to the JESD204B subsystem and the other to interface to the Platform Designer (Standard) components (core PLL reconfiguration controller and SPI master modules) in the top level Platform Designer (Standard) project.
  • PIO (altera_avalon_pio)—provides general input/output (I/O) access from the Nios II processor to the HDL components in the FPGA via two sets of 32-bit registers:
    • io_status—status registers input from the HDL components to the Nios II processor
    • io_control—control registers output from the Nios II processor to the HDL components

The tables below describe the signal connectivity for the io_status and io_control registers.

Table 36.   Signal Connectivity for io_status Registers
Bit Signal
0 Core PLL locked
1 TX transceiver ready (Link 0)
2 RX transceiver ready (Link 0)
3 Test pattern checker data error (Link 0)
4–31 TX transceiver ready, RX transceiver ready, and test pattern checker data error signals for subsequent links, if present.
Table 37.   Signal Connectivity for io_control Registers
Bit Signal
0 RX serial loopback enable for lane 0 (Link 0)
1 RX serial loopback enable for lane 1 (Link 0)
2 RX serial loopback enable for lane 2 (Link 0)
3 RX serial loopback enable for lane 3 (Link 0)
4–30 RX serial loopback enable for subsequent links, if present.
31 Sysref (Not implemented in software)

You can access the address map of the submodules in the Nios II subsystem by clicking on the Address Map tab in the Platform Designer (Standard) window.

18 Note that Platform Designer (Standard) does not allow multiple Platform Designer (Standard) systems with the same name in the same project. If you have a Platform Designer (Standard) system with the same name, please change the name of your Platform Designer (Standard) system.

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