18.104.22.168. Implementing a Multi-Link Design
In the top level HDL file, each link in a JESD204B multi-link use case corresponds to an instantiation of a transport layer TX and RX pair and a pattern generator and checker pair (assuming duplex data path configuration). The HDL file uses the Verilog generate statement using the system parameter LINK as an index variable to generate the requisite number of instances for the multi-link use case. This section assumes that each transport layer TX and RX pair and pattern generator and checker pair in the multi-link design has identical parameter configurations. In the software C code, all software tasks are coded with multi-link capabilities. The MAX_LINKS software parameter in the main.h header file defines the number of links in the design. In a multi-link scenario, each software action performs an identical task on each link starting with link 0 and proceeding sequentially until the link indicated by the MAX_LINKS parameter.
- Edit the Platform Designer (Standard) project.
- Edit the top level HDL file.
- Edit the software C code.
The following sections describe these procedures in detail.
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